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參數(shù)資料
| 型號： | GS9025A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Digital Receiver |
| 中文描述： | 串行數(shù)字接收機(jī) |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 192K |
| 代理商： | GS9025A |
GENNUM CORPORATION
522 - 75 - 00
10
G
other TTL/CMOS compatible logic inputs. In addition, when
loss of carrier is detected, the SDO/SDO outputs are muted
(set to a known static state).
1-2. Carrier Detect Threshold Adjust
This feature has been designed for use in applications such
as routers where signal crosstalk and circuit noise cause
the equalizer to output erroneous data when no input signal
is present. The use of a Carrier Detect function with a fixed
internal reference does not solve this problem since the
signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set
by the on chip reference. To alleviate this problem, the
GS9025A provides a user adjustable threshold to meet the
unique conditions that exist in each user's application.
Override and internal default settings have also been
provided to give the user total flexibility.
The threshold level at which loss of carrier is detected is
adjustable via external resistors at the CD_ADJ pin. The
control voltage at the CD_ADJ pin is set by a simple resistor
divider circuit (see Typical Application Circuit). The
threshold level is adjustable from 200m to 350m. By default
(no external resistors), the threshold is typically 320m. In
noisy environments, it is not recommended to leave this pin
floating. Connecting this pin to V
EE
disables the SDO/SDO
muting function and allows for maximum possible cable
length equalization.
1-3. Output Eye Monitor Test
The GS9025A also provides an 'Output Eye Monitor Test'
(OEM_TEST) which allows the verification of signal integrity
after equalization, prior to reslicing. The OEM_TEST pin is
an open collector current output that requires an external
50
pullup resistor. When the pullup resistor is not used,
the OEM_TEST block is disabled and the internal
OEM_TEST circuit is powered down. The OEM_TEST
provides a 100mVp-p
signal when driving a 50
oscilloscope input. Due to additional power consumed by
this diagnostic circuit, it is not recommended for continuous
operation.
2. RECLOCKER
The reclocker receives a differential serial data stream from
the internal multiplexer. It locks an internal clock to the
incoming data. It outputs the differential PECL retimed data
signal on SDO/SDO. It outputs the recovered clock on SCO/
SCO. The timing between the output and clock signals is
shown in Figure 17.
Fig. 17 Output and Clock Signal Timing
The reclocker contains four main functional blocks: the
Phase Locked Loop, Auto/Manual Data Rate Select,
Frequency Acquisition, and Logic Circuit.
2-1. Phase Locked Loop (PLL)
The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.
Fig. 18 Simplified Block Diagram of the PLL
2-2. VCO
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO centre frequency. The VCO
operates between 30 and 540Mb/s and has a pull range of
±15% about the centre frequency. A single low impedance
external resistor, R
VCO
, sets the VCO centre frequency (see
Figure 19). The low impedance R
VCO
minimizes thermal
noise and reduces the PLL's sensitivity to PCB noise.
For a given R
VCO
value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO centre
frequency corresponds to the
L
curve. For all other
SMPTE/SS0 combinations, the VCO centre frequency
corresponds to the
H
curve (
H
is approximately 1.5 x
L
).
SDO
SCO
50%
DDI/DDI
LF+
LFS
LF-
R
VCO
VCO
DIVISION
R
LF
C
LF1
C
LF2
2
PHASE
DETECTOR
INTERNAL
PLL CLOCK
CHARGE
PUMP
LOOP
FILTER
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