GENNUM CORPORATION
22208 - 0
39 of 47
G
3.11 PARALLEL DATA OUTPUTS
Data outputs leave the device on the rising edge of PCLK
as shown in Figure 13.
The data may be scrambled or unscrambled, framed or
unframed, and may be presented in 10-bit or 20-bit format.
The output data bus width is controlled independently from
the internal data bus width by the 20bit/10bit input pin.
Likewise, the output data format is defined by the setting of
the external SMPTE_BYPASS and DVB_ASI pins. Recall that
these pins are set by the application layer as inputs to the
device.
3.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS9060 are driven by high-
impedance buffers which support both LVTTL and LVCMOS
levels. These buffers use a separate power supply of +3.3V
DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven
to a high-impedance state if the RESET_TRST signal is
asserted LOW.
Figure 13 PCLK to Data Timing
TABLE 14 HOST INTERFACE DESCRIPTION FOR EDH FLAG REGISTER
REGISTER NAME
BIT
NAME
DESCRIPTION
R/W
DEFAULT
EDH_FLAG
Address: 03h
15
Not Used
14
ANC-UES out
Ancillary Unknown Error Status Flag.
R
0
13
ANC-IDA out
Ancillary Internal device error Detected Already Flag.
R
0
12
ANC-IDH out
Ancillary Internal device error Detected Here Flag.
R
0
11
ANC-EDA out
Ancillary Error Detected Already Flag.
R
0
10
ANC-EDH out
Ancillary Error Detected Here Flag.
R
0
9
FF-UES out
Full Field Unknown Error Status Flag.
R
0
8
FF-IDA out
Full Field Internal device error Detected Already Flag.
R
0
7
FF-IDH out
Full Field Internal device error Detected Here Flag.
R
0
6
FF-EDA out
Full Field Error Detected Already Flag.
R
0
5
FF-EDH out
Full Field Error Detected Here Flag.
R
0
4
AP-UES out
Active Picture Unknown Error Status Flag.
R
0
3
AP-IDA out
Active Picture Internal device error Detected Already Flag.
R
0
2
AP-IDH out
Active Picture Internal device error Detected Here Flag.
R
0
1
AP-EDA out
Active Picture Error Detected Already Flag.
R
0
0
AP-EDH out
Active Picture Error Detected Here Flag.
R
0
PCLK
DOUT[19:0]
DATA
Control signal
output
t
OH
t
OD