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參數(shù)資料
| 型號： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 40/47頁 |
| 文件大小： | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
40 of 47
G
3.11.2 Parallel Output in SMPTE Mode
When the device is operating in SMPTE mode, (see Section
3.7), data may be presented to the output bus in either
multiplexed or demultiplexed form depending on the setting
of the 20bit/10bit input pin.
In 20-bit mode, (20bit/10bit = HIGH), the output data will be
word aligned, demultiplexed luma and chroma data. Luma
words will always appear on DOUT[19:10] while chroma
words will occupy DOUT[9:0].
In 10-bit mode, (20bit/10bit = LOW), the output data will be
word aligned, multiplexed luma and chroma data. The data
will be presented on DOUT[19:10], and the device will force
DOUT[9:0] LOW.
3.11.3 Parallel Output in DVB-ASI Mode
When operating in DVB-ASI mode, (see Section 3.8), the
GS9060 automatically configures the output port for 10-bit
operation regardless of the setting of the 20bit/10bit pin.
The extracted 8-bit data words will be presented on
DOUT[17:10] such that DOUT17 = HOUT is the most
significant bit of the decoded transport stream data and
DOUT10 = AOUT is the least significant bit.
In addition, DOUT19 and DOUT18 will be configured as the
DVB-ASI status signals SYNCOUT and WORDERR
respectively. See Section 3.8.2 for a description of these
DVB-ASI specific output signals.
DOUT[9:0] will be forced LOW when the GS9060 is
operating in DVB-ASI mode.
3.11.4 Parallel Output in Data-Through Mode
When operating in Data-Through mode, (see Section 3.9),
the GS9060 presents data to the output data bus without
performing any decoding, descrambling or word-alignment.
3.11.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS9060 is
determined by the output data format. Table 15 below lists
the possible output signal formats and their corresponding
parallel clock rates. Note that DVB-ASI output will always be
in 10-bit format, regardless of the setting of the 20bit/10bit
pin.
TABLE 15 PARALLEL DATA OUTPUT FORMAT
OUTPUT DATA FORMAT
INPUT CONTROL SIGNALS
DOUT
[19:10]
DOUT
[9:0]
PCLK
20bit/10bit
SMPTE_BYPASS
DVB_ASI
SMPTE MODE
20bit DEMULTIPLEXED
HIGH
HIGH
LOW
LUMA
CHROMA
13.5MHz
10bit MULTIPLEXED
LOW
LUMA / CHROMA
FORCED LOW
27MHz
DVB-ASI MODE
10bit DVB-ASI
HIGH
LOW
HIGH
DVB-ASI DATA
FORCED LOW
27MHz
LOW
DATA-THROUGH MODE
20bit DEMULTIPLEXED
HIGH
LOW
LOW
DATA
DATA
13.5MHz
10bit MULTIPLEXED
LOW
DATA
FORCED LOW
27MHz
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