參數(shù)資料
型號: GTL2010BS
廠商: NXP SEMICONDUCTORS
元件分類: 其它接口
英文描述: 10-bit bidirectional low voltage translator
中文描述: SPECIALTY INTERFACE CIRCUIT, DSO24
封裝: 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-616-1, HVQFN-24
文件頁數(shù): 3/20頁
文件大?。?/td> 117K
代理商: GTL2010BS
GTL2010_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 3 March 2008
3 of 20
NXP Semiconductors
GTL2010
10-bit bidirectional low voltage translator
6.
Pinning information
6.1 Pinning
6.2 Pin description
[1]
HVQFN24 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Fig 2.
Pin configuration for TSSOP24
Fig 3.
Pin configuration for HVQFN24
GTL2010PW
GND
GREF
SREF
DREF
S1
D1
S2
D2
S3
D3
S4
D4
S5
D5
S6
D6
S7
D7
S8
D8
S9
D9
S10
D10
002aac057
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
002aac058
GTL2010BS
Transparent top view
D7
S6
S7
D6
S5
D5
S4
D4
S3
D3
S2
D2
S
S
S
D
D
D
S
S
G
G
D
D
terminal 1
index area
6
13
5
14
4
15
3
16
2
17
1
18
7
8
9
1
1
1
2
2
2
2
2
1
Table 3.
Symbol
Pin description
Pin
TSSOP24
1
2
3, 4, 5, 6, 7, 8, 9,
10, 11, 12
22, 21, 20, 19, 18,
17, 16, 15, 14, 13
23
24
Description
HVQFN24
22
[1]
23
24, 1, 2, 3, 4, 5, 6,
7, 8, 9
19, 18, 17, 16, 15,
14, 13, 12, 11, 10
20
21
GND
SREF
S1 to S10
ground (0 V)
source of reference transistor
Port S1 to Port S10
D1 to D10
Port D1 to Port D10
DREF
GREF
drain of reference transistor
gate of reference transistor
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