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參數(shù)資料
| 型號(hào)： | GTLP16612MTD |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UNIV BUS TXRX 18BIT 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 系列： | 74GTLP |
| 邏輯類型： | 通用總線收發(fā)器 |
| 電路數(shù)： | 18 位 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
www.fairchildsemi.com
2
GTLP16612
Pin Descriptions
Connection Diagram
Functional Description
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A Port and control pins
operate at LVTTL or 5V TTL levels while the B Port operates at GTLP levels. The transceiver logic includes D-type latches
and D-type flip-flops to allow data flow in transparent, latched and clock mode.
The functional operation is described in the truth table below.
Truth Table
(Note 1)
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
Pin
Names
Description
OEAB
A-to-B Output Enable (Active LOW)
OEBA
B-to-A Output Enable (Active LOW)
CEAB
A-to-B Clock Enable (Active LOW)
CEBA
B-to-A Clock Enable (Active LOW)
LEAB
A-to-B Latch Enable (Transparent HIGH)
LEBA
B-to-A Latch Enable (Transparent HIGH)
CLKAB
A-to-B Clock Pulse
CLKBA
B-to-A Clock Pulse
VREF
GTLP Input Reference Voltage
A1–A18
A-to-B TTL Data Inputs or
B-to-A 3-STATE Outputs
B1–B18
B-to-A GTLP Data Inputs or
A-to-B Open Drain Outputs
Inputs
Output
Mode
CEAB
OEAB
LEAB
CLKAB
A
B
X
H
X
Z
Latched
LLL
H
X
B0(Note 2)
storage
LLLL
X
B0(Note 3)
of A data
X
L
H
X
L
Transparent
XL
H
X
H
LLL
↑
L
Clocked storage
LLL
↑
H
of A data
HL
L
X
B0(Note 3)
Clock inhibit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTLP16612MTD_Q | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16612MTDX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLP16616 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:17-Bit TTL/GTLP Bus Transceiver with Buffered Clock |
| GTLP16616B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| GTLP16616MEA | 功能描述:總線收發(fā)器 18-Bit Univ Bus Tran RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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