參數(shù)資料
型號(hào): GTLP16616MTDX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 1/9頁(yè)
文件大小: 0K
描述: IC TRANSCVR 17BIT N-INV 56TSSOP
標(biāo)準(zhǔn)包裝: 1,000
邏輯類型: 收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 17
輸出電流高,低: 32mA,32mA
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
2000 Fairchild Semiconductor Corporation
DS500017
www.fairchildsemi.com
June 1997
Revised December 2000
GTLP166
16
17-
Bit
T
TL/GTLP
B
u
s
T
ranscei
ver
wit
h
Buf
fer
ed
Cl
ock
GTLP16616
17-Bit TTL/GTLP Bus Transceiver
with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that
provides TTL to GTLP signal level translation. It allows for
transparent, latched and clocked modes of data flow and
provides a buffered GTLP (CLKOUT) clock output from the
TTL CLKAB. The device provides a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (
<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic
levels
s Designed with edge rate control circuitry to reduce
output noise on the GTLP port
s VREF pin provides external supply reference voltage for
receiver threshold adjustibility
s Special PVT compensation circuitry to provide
consistent performance over variations of process,
supply voltage and temperature
s TTL compatible driver and control inputs
s Designed using Fairchild advanced CMOS technology
s Bushold data inputs on the A port eliminates the need
for external pull-up resistors on unused inputs.
s Power up/down and power off high impedance for live
insertion
s 5 V tolerant inputs and outputs on the LVTTL ports
s Open drain on GTLP to support wired-or connection
s Flow through pinout optimizes PCB layout
s D-type flip-flop, latch and transparent data paths
s A Port source/sink
32 mA/+32 mA
s GTLP Buffered CLKAB signal available (CLKOUT)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
GTLP16616MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
GTLP16616MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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GTLP16617 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
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GTLP16617MEAX 功能描述:總線收發(fā)器 17-Bit Syn Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
GTLP16617MTD 功能描述:總線收發(fā)器 17-Bit Syn Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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