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參數(shù)資料
| 型號： | GTLP8T306MTC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit LVTTL/GTLP Bus Transceiver |
| 中文描述： | GTLP SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 4.40 MM, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 56K |
| 代理商： | GTLP8T306MTC |
2000 Fairchild Semiconductor Corporation
DS500051
www.fairchildsemi.com
September 1997
Revised December 2000
G
GTLP8T306
8-Bit LVTTL/GTLP Bus Transceiver
General Description
The GTLP8T306 is an 8-bit bus transceiver that provides
LVTTL to GTLP signal level translation. The device pro-
vides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (
<
1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal output edge-rate control and
is process, voltage, and temperature (PVT) compensated.
Its function is similar to BTL and GTL but with different out-
put levels and receiver thresholds. The GTLP output LOW
level is typically less than 0.5V, the output HIGH level is
1.5V and the receiver threshold is 1.0V.
Features
I
Bidirectional interface between GTLP and LVTTL logic
levels
I
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
I
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
I
Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
I
TTL compatible driver and control inputs
I
Designed using Fairchild advanced CMOS technology
I
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
I
Power up/down and power off high impedance for live
insertion
I
5V over voltage tolerance on LVTTL ports
I
Open drain on GTLP to support wired-or connection
I
Flow through pinout optimizes PCB layout
I
A Port source/sink
24mA/
+
24mA
I
B Port sink
+
50mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Connection Diagram
Order Number
GTLP8T306MTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTLP8T306MTCX | 功能描述:總線收發(fā)器 8-Bit Bus Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| GTLPBT306MTCX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| GTLPH1612 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER |
| GTLPH16612DGG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| GTLPH16612DL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
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