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參數(shù)資料
| 型號(hào)： | H06 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Inverter with open-drain outputs |
| 中文描述： | 漏極開(kāi)路輸出的反相器 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | H06 |
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2003 Dec 02
2
Philips Semiconductors
Product specification
Inverter with open-drain outputs
74HC3G06; 74HCT3G06
FEATURES
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Low power dissipation
SOT505-2 and SOT765-1 package
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74HC3G06/74HCT3G06 is a high-speed Si-gate
CMOS device. Specified in compliance with JEDEC
standard no. 7A.
The 74HC3G06/74HCT3G06 provides three inverting
buffers.
The outputs of the 74HC3G06; 74HCT3G06 devices are
open drains and can be connected to other open-drain
outputs to implement active-LOW wired-OR or
active-HIGH wired-AND functions. For digital operation
this device must have a pull-up resistor to establish a logic
HIGH-level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
6.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
For 74HC3G06 the condition is V
I
= GND to V
CC
.
For 74HCT3G06 the condition is V
I
= GND to V
CC
1.5 V.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC3G
HCT3G
t
PZL
t
PLZ
C
I
C
PD
propagation delay nA to nY
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer
C
L
= 50 pF; V
CC
= 4.5 V
C
L
= 50 pF; V
CC
= 4.5 V
9
11
1.5
4
9
12
1.5
4
ns
ns
pF
pF
notes 1 and 2
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