參數(shù)資料
型號(hào)： H25PL12S
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： XO, clock
英文描述： PLL FREQUENCY SYNTHESIZER
文件頁(yè)數(shù)： 17/17頁(yè)
文件大?。?/td> 235K
代理商： H25PL12S
H25PL12S
Data Sheet
9/ 17
2004 Hynix Semiconductor Inc. All rights reserved.
(6) Bypass mode
H25PL12S has bypass mode for test main block of chip. When bypass signal and
tdm is active(active high), PLL output clock is bpck.
(7) digital block test mode
At mass product test, H25PL12S provided digital block test. When tdm is
active(active high), bpck clock is provided to whole digital block in H25PL12S and
check mc[13:0] and ncb[7:0] .And if cnttest is high, internal counter is toggle
each bit by m, or n.
H25PL12S
lfo
External
VCO
vcon
vck
ref
ck
bpck
tdm
“1”
vcopd
Figure 2. External VCO configuration block diagram
At this mode, frequency of ck is determined by section 1.a), and frequency of vck is
determined by section 1.b)
(8) VCO block and Charge pump test mode
At mass product test, tpdud[1:0] control the VCO control voltage directly for
getting VCO gain and charge pump up or down current.
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