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參數(shù)資料
| 型號： | H606125X8S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3 V Self Recovering Watchdog |
| 中文描述： | 3伏自我恢復看門狗 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 142K |
| 代理商： | H606125X8S |
H6061
5
Pin Description
Pin Name
1
V
2
3
RC
4
V
SS
5
6
7
RES
8
V
DD
Table 6
Functional Description
Thresholds and Outputs
The H6061 has open-drain outputs and voltage
thresholds on pin V
IN
of typically 1.5 V.
Internal Voltage Comparators
The voltage comparators detect the voltage applied to
pin V
and compare it with thresholds V
, V
and V
.
The H6061 is designed for monitoring regulated DC
voltages and has bandgap thresholds independent of
V
. The reaction of the H6061 to voltage changes on
pin V
is given in Fig. 4. During powering-up, the
outputs are active. After V
reaches the V
level, pin
SAVE deactivates after a short debounce time T
to
allow for fast ramp-ups. The initialization time T
then
passes before the two reset outputs go inactive.
Thereafter, when the voltage on pin V
falls below the
V
SL
level, pin SAVE goes active low as a first warning. If
V
then drops below the V
level, the reset signals go
active and are guaranteed down to 1.6 V. The reset
outputs react also to timeouts (see “Timer clearing”).
Note that when the supply voltage V
is below the level
V
(about 2.2 V), all outputs are in the active state for
any allowed voltage of V
IN
.
Voltage Programming
The H6061 was designed to give the best compromise
in normal usage (see Table 3). Its voltage threshold can
be programmed by an external resistor divider or a
potentiometer to react at proportionally higher voltage
levels (see Fig. 8 below).
Voltage Programming
Function
Voltage monitoring input
Timer clear input signal
RC oscillator tuning input
GND terminal
Reset output, open drain
Save output, open drain
Positive reset output, open drain
Positive supply voltage
Timer Programming
A single timeout period T
is used for the initialization
reset duration and the watchdog timeout. With pin RC
unconnected, the on-chip RC oscillator and divider chain
give a timeout period T
of typically 100 ms. A resistor
to V
will shorten this time, and a capacitor to V
will
lengthen it (see Fig. 11). An approximation for
calculating trial values given in milliseconds by the
formula:
+
+
=
V
4.8
R
= 10 k
, C
= 1
μ
F
If R
1
is in M
and C
1
in pF, T
TO
will be in ms.
Choice of component values must be determined in
practice. To have a square wave of period 2T
, simply
connect pin TCL to V
DD
or V
SS
and take the signal output
from a reset pin.
Timer Clearing
A negative edge or pulse at the TCL input longer than
150 ns will clear the timer and deactivate the reset
outputs under normal running conditions (see Fig. 3).
TCL will however have no effect either when V
<
V
or
during the initialization period before the deactivation of
the reset pins.
Combined Voltage and Timer Action
In Fig. 6 is a typical sequence of power-up, watchdog
run, and power-down. During initialization the SAVE pin
deactivates one debounce delay time T
after V
rises
above V
, or when the power line V
rises above V
,
whichever happens last. The reset pins only deactivate
one timeout period T
afterwards to free the watchdog
timer and end the initialization. Note that either V
falling
below V
threshold or V
below V
will cause an
initialization upon recovery. Following initialization, the
watchdog timer will time out after time T
unless at least
one TCL pulse clears it. On timeout the reset pins
reactivate for a further T
period before deactivating
again for another try. A TCL pulse will deactivate any
timeout reset, and another TCL pulse must follow within
a time T
to keep reset inactive. If no TCL pulses come
at all, the reset pins go square-wave. Power-down
overrides all this however. A falling voltage on V
gives a
warning SAVE = 0 signal at V
IN
= V
before activating
the reset pins as soon as V
drops below V
. The
H6061 has fixed thresholds and low hysteresis for
monitoring regulated DC lines. Additional protection is
provided in case V
supply falls over about 10% below
V
ON
which thereupon activates all outputs at once.
TCL
RES
SAVE
H
V
DD
+3 V / +5 V
V
IN
V
SS
Fig. 8
192
.
6
0.8
-
)
+
R
C
(32
0.75
1
DD
1
TO
T
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