
865
HICR0—Host Interface Control Register 0
H'FE40
HIF (LPC)
7
LPC3E
0
R/W
—
6
LPC2E
0
R/W
—
5
LPC1E
0
R/W
—
4
FGA20E
0
R/W
—
3
SDWNE
0
R/W
—
0
LSCIE
0
R/W
—
2
PMEE
0
R/W
—
1
LSMIE
0
R/W
—
Bit
Initial value
Slave Read/Write
Host Read/Write
LSCI output enable
HICR0
Bit 0
LSCIB
LSCIE
0
HICR1
Bit 0
0
1
0
1
Description
LSCI output disabled, other function of pin enabled
LSCI output disabled, other function of pin enabled
LSCI output enabled, LSCI pin output goes to 0 level
LSCI output enabled, LSCI pin output is high-impedance
1
LSMI output enable
HICR0
Bit 1
LSMIB
LSMIE
0
HICR1
Bit 1
0
1
0
1
Description
LSMI output disabled, other function of pin enabled
LSMI output disabled, other function of pin enabled
LSMI output enabled,
LSMI
pin output goes to 0 level
LSMI output enabled,
LSMI
pin output is high-impedance
1
PME output enable
HICR0
Bit 2
PMEB
PMEE
0
HICR1
Bit 2
0
1
0
1
Description
PME output disabled, other function of pin enabled
PME output disabled, other function of pin enabled
PME output enabled,
PME
pin output goes to 0 level
PME output enabled,
PME
pin output is high-impedance
1
Fast GATE A20 enable
0
Fast GATE A20 function is disabled
Other function of pin is enabled
GA20 output internal state is initialized to 1
1
Fast GATE A20 function is enabled
GA20 pin output is open-drain (external VCC pull-up resistor required)
LPC enable 1
0
LPC channel 1 operation is disabled
No address (H'0060, 64) matches for IDR1, ODR1, or STR1
1
LPC channel 1 operation is enabled
LPC enable 2
0
LPC channel 2 operation is disabled
No address (H'0062, 66) matches for IDR2, ODR2, or STR2
1
LPC channel 2 operation is enabled
LPC enable 3
0
LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15
1
LPC channel 3 operation is enabled
LPC software shutdown enable
0
Normal state, LPC software shutdown setting enabled
[Clearing conditions]
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown release (rising edge of
LPCPD
signal)
1
LPC hardware shutdown state setting enabled
Hardware shutdown state when
signal is low
[Setting condition]
Writing 1 after reading SDWNE = 0