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參數(shù)資料
| 型號(hào)： | MH64D72KLG-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 中文描述： | 4831838208位（67108864 - Word的72位），雙數(shù)據(jù)速率同步DRAM模塊 |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MH64D72KLG-10 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0389-1.1
20.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
8
FUNCTION TRUTH TABLE (continued)
Current State
/S0
/RAS /CAS
/WE
Address
Command
Action
WRITE
(Auto-
Precharge
Disabled)
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
L
H
H
H
H
H
L
X
BA
NOP
TERM
NOP (Continue Burst to END)
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin Read, Determine Auto-
Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
L
L
H
L
L
H
BA, A10
X
PRE / PREA
REFA
Terminate Burst, Precharge
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
WRITEA
L
H
L
L
BA, CA, A10
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
L
L
L
H
X
Op-Code,
Mode-Add
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Notes
3
3
2
2
2
2
2
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PDF描述 |
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| MH64D72KLG-75 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64S64APFH-6 | 4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH64D72KLG-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64D72KLH-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| MH64FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
| MH64FAD-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator |
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