xvii
25.3.4 Timing of On-Chip Supporting Modules............................................................. 754
A/D Conversion Characteristics........................................................................................ 764
D/A Conversion Characteristics........................................................................................ 765
25.6 Flash Memory Characteristics........................................................................................... 766
25.7
Usage Note (Internal Step-Down)..................................................................................... 768
25.4
25.5
Appendix A Instruction Set
............................................................................................... 769
A.1
Instruction.......................................................................................................................... 769
A.2
Instruction Codes............................................................................................................... 787
A.3
Operation Code Map.......................................................................................................... 801
A.4
Number of States Required for Execution......................................................................... 805
A.5
Bus States During Instruction Execution .......................................................................... 818
Appendix B Internal I/O Registers
.................................................................................. 834
B.1
Addresses........................................................................................................................... 834
B.2
Register Selection Conditions............................................................................................ 843
B.3
Functions............................................................................................................................ 853
Appendix C I/O Port Block Diagrams
........................................................................... 952
C.1
Port 1 Block Diagram........................................................................................................ 952
C.2
Port 2 Block Diagrams ...................................................................................................... 953
C.3
Port 3 Block Diagram........................................................................................................ 956
C.4
Port 4 Block Diagrams ...................................................................................................... 959
C.5
Port 5 Block Diagrams ...................................................................................................... 966
C.6
Port 6 Block Diagrams ...................................................................................................... 969
C.7
Port 7 Block Diagrams ...................................................................................................... 974
C.8
Port 8 Block Diagrams ...................................................................................................... 975
C.9
Port 9 Block Diagrams ...................................................................................................... 982
C.10 Port A Block Diagrams...................................................................................................... 987
C.11 Port B Block Diagram ....................................................................................................... 990
C.12 Port C, D, E, F, G Block Diagram..................................................................................... 993
Appendix D Pin States
........................................................................................................ 994
D.1
Port States in Each Processing State.................................................................................. 994
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode
................................................................................................ 996
E.1
Timing of Transition to Hardware Standby Mode............................................................ 996
E.2
Timing of Recovery from Hardware Standby Mode......................................................... 996