參數(shù)資料
型號(hào)： HA16117FPCJ
廠商： Hitachi,Ltd.
英文描述： CMOS Watchdog Timer
中文描述： 看門(mén)狗定時(shí)器的CMOS
文件頁(yè)數(shù)： 7/31頁(yè)
文件大小： 249K
代理商： HA16117FPCJ
HA16117F Series
7
Internal Operation and Usage Notes
Figure 3 shows an equivalent circuit of the watchdog timer block with a V
CC
pin level of 5 V and ACC pin
level of 0 V, and the following pages show internal operation timing charts for different P-RUN
frequencies. (Descriptions apply to conditions C
F
= 0.01
μ
F, C
R
= 0.1
μ
F, R
2
/(R
1
+ R
2
) = 0.6.)
Operation
The power-on and auto-reset circuit is a multivibrator with timing controlled by C
R
charge current I
1
and
discharge current I
2
. As I
1
: I
2
≈
3 : 1 (Typ design value), when the (WD) (watchdog filter circuit output)
on-duty is 25% or above, the C
R
pin potential does not fall below 1.6 V. Therefore, (C) in the figure below
is fixed low, and
RES
is not output. The (WD) on-duty varies according to the P-RUN frequency. If the
frequency is lower or higher than the design value, the (WD) on-duty decreases, and at 25% or below,
RES
is output. Refer to the timing charts on the following pages for an explanation of the operation of the
watchdog filter.
Usage Notes
When the P-RUN frequency reaches 20 kHz or above, t
OFF
is short (see the timing charts on the
following pages). This must be borne in mind in the design stage.
If the P-RUN frequency fluctuates,
RES
may also be output within the normal detection set frequency
(see the timing charts on the following pages).
Detection frequencies f
H
and f
L
described in the Data Book are Typ values, and a certain amount of
dispersion can be expected. A margin of
±
30% or more should be allowed for in the design.
+
+
+
A
I
w
0.8
μ
typ
C
F
0.01
μ
0.1
μ
P-RUN
1/2
frequency divider
0.9 V
3.6 V
WD
B
C
I
10.7
μ
typ
I
1
8
μ
typ
Q
D
φ
Q
3.2 V
1.6 V
Low voltage detection block
Power-on and auto-reset circuit
Watchdog filter circuit
C
R
V
CC
(5 V)
RES
Q
Q
Figure 3 Watchdog Timer Evaliation Circuit
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