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參數(shù)資料
| 型號(hào)： | HA3-2405-5 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 40MHz, PRAM Four Channel Programmable Amplifiers |
| 中文描述： | OP-AMP, 11000 uV OFFSET-MAX, 8 MHz BAND WIDTH, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | HA3-2405-5 |
3-163
Schematic Diagram
HA-2400
Settling Time (Notes 4, 5, 9)
V
OUT
= 10V
P-P
25
-
1.5
2.5
-
1.5
2.5
μ
s
CHANNEL SELECT CHARACTERISTICS
Digital Input Current
V
IN
= 0V
V
IN
= +5.0V
Full
-
1
1.5
-
1
1.5
mA
Digital Input Current
Full
-
5
-
-
5
-
nA
Output Delay (Notes 6, 9)
25
-
100
250
-
100
250
ns
Crosstalk (Note 7)
25
-80
-110
-
-74
-110
-
dB
POWER SUPPLY CHARACTERISTICS
Supply Current
25
-
4.8
6.0
-
4.8
6.0
mA
Power Supply Rejection Ratio
V
S
=
±
10V to
±
20V
Full
74
90
-
74
90
-
dB
NOTES:
3. A
V
= +10, C
COMP
= 0, R
L
= 2k
, C
L
= 50pF.
4. A
V
= +1, C
COMP
= 15pF, R
L
= 2k
, C
L
= 50pF.
5. To 0.1% of final value.
6. To 10% of final value; output then slews at normal rate to final value.
7. Unselected input to output; V
IN
=
±
10V
DC
.
8. Unselected channels have approximately the same input parameters.
9. Guaranteed by design.
10. Full Power Bandwidth based on slew rate measurement using:
11. See Figure 13 for test circuit.
.
Electrical Specifications
Test Conditions: V
SUPPLY
=
±
15V, Unless Otherwise Specified. Digital Inputs: V
IL
= +0.5V, V
IH
= +2.4.
Limits apply to each of the four channels, when addressed
(Continued)
PARAMETER
TEST
CONDITIONS
TEMP.
(
o
C)
HA-2400/04
HA-2405
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
FPBW
--------------------------
VPEAK
;
5V
=
=
E
GND
OUT
R
31
36.5
R
2
2.4K
R
4
22.9K
Q
1
Q
3
Q
4
Q
6
Q
7
Q
8
R
1
1.6K
R
3
1.8K
Q
2
Q
5
R
5
8.0K
R
6
2.0K
R
35
1.6K
R
7
5.6K
Q
10
Q
11
Q
13
Q
12
Q
15
Q
14
R
8
4K
Q
16
R
9
1.5K
R
10
10K
R
11
10K
VA
VC
Q17
VB
Q
18
Q
19
Q
20
VD
R
12
1.6K
Q
28
VE
R
13
0.8K
Q
22
R
15
10K
R
16
10K
Q
21
Q
26
Q
27
R
14
10K
Q
29
Q
23
Q
24
Q
25
Q
30
Q
32
Q
33
Q
102
Q
34
Q
38
R
18
2.0K
Q
103
Q
35
Q
31
Q
36
Q
37
Q
39
Q
40
Q
41
Q
79
Q
81
Q
84
Q
82
Q
80
Q
83
Q
86
Q
89
Q
88
R
35
0.75K
Q
85
Q
98
Q
92
R
30
1.2K
C
1
9.0pF
V+
Q
93
Q
42
R19
1.6K
TO ADDITIONAL
INPUT STAGES
R
29
0.4K
Q
90
Q
91
R
33
4K
Q
97
Q
100
Q
99
Q
95
Q
94
+V
CC
-V
EE
R
32
34
Q
96
COMP
IN-
IN+
D1
D0
R
17
1.6K
Q
87
R
34
1.6K
Q
101
Q
9
Diagram Includes: One Input Stage, Decode Control, Bias Network, and Output Stage
HA-2400, HA-2404, HA-2405
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