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參數(shù)資料
| 型號： | HA7-2645-5 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP 4MHZ HIGH VOLT 8-DIP |
| 標準包裝： | 48 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉換速率： | 5 V/µs |
| 增益帶寬積： | 4MHz |
| 電流 - 輸入偏壓： | 12nA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 3.2mA |
| 電流 - 輸出 / 通道： | 12mA |
| 電壓 - 電源，單路/雙路(±)： | 20 V ~ 80 V，±10 V ~ 40 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-CDIP（0.300"，7.62mm） |
| 供應商設備封裝： | 8-CERDIP |
| 包裝： | 管件 |
8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2904.5
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
bbb
C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
S
ccc
C A - B
M
D
S
aaa
CA - B
M
D
S
eA
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N8
8
Rev. 0 4/94
HA-2640, HA-2645
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HA7-2645-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HA7-2650-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HA7-2650-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HA7-2655-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HA7-2720-8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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