參數(shù)資料
型號(hào): HA7-5137883
廠商: Intersil Corporation
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 60MHz, Ultra Low Noise, Precision Operational Amplifier
中文描述: 60MHz時(shí),超低噪聲,精密運(yùn)算放大器
文件頁數(shù): 8/8頁
文件大小: 100K
代理商: HA7-5137883
8
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Spec Number
511034-883
HA-5137/883
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j
x 45
o
D3
B
h x 45
o
A
A1
E
L
L3
e
B3
L1
D2
D1
e
1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010
E H
S
S
0.010
E F
S
S
-E-
0.007
E F
M
S H S
B1
-H-
-F-
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
A
A1
B
B1
B2
B3
D
D1
D2
D3
E
E1
E2
E3
e
e1
h
j
L
L1
L2
L3
ND
NE
N
INCHES
MIN
0.060
0.050
-
0.022
0.072 REF
0.006
0.342
0.200 BSC
0.100 BSC
-
0.342
0.200 BSC
0.100 BSC
-
0.050 BSC
0.015
0.040 REF
0.020 REF
0.045
0.045
0.075
0.003
MILLIMETERS
MIN
1.52
1.27
-
0.56
1.83 REF
0.15
8.69
5.08 BSC
2.54 BSC
-
8.69
5.08 BSC
2.54 BSC
-
1.27 BSC
0.38
1.02 REF
0.51 REF
1.14
1.14
1.91
0.08
5
5
20
NOTES
6, 7
-
-
2, 4
-
-
-
-
-
2
-
-
-
2
-
2
5
5
-
-
-
-
3
3
3
MAX
0.100
0.088
-
0.028
MAX
2.54
2.23
-
0.71
0.022
0.358
0.56
9.09
0.358
0.358
9.09
9.09
0.358
9.09
-
-
0.055
0.055
0.095
0.015
1.40
1.40
2.41
0.38
5
5
20
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
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