HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
Rev.0.02, Sep.15.2004, page 69 of 89
Identifier
Included
in resp
Type
Value
Description
Clear
condition
Illegal command R1 R2
E R
‘
0
’
= no error
‘
1
’
= error
Command not legal for the card state C
Card ECC failed R2
DataErr
E X
‘
0
’
= success
‘
1
’
= failure
Card internal ECC was applied but
failed to correct the data.
C
CC error
R2
DataErr
E R X
‘
0
’
= no error
‘
1
’
= error
Internal card controller error
C
Error
R2
DataErr
E R X
‘
0
’
= no error
‘
1
’
= error
A general or an unknown error
occurred during the operation.
C
WP erase skip
R2
S X
‘
0
’
= not protected
‘
1
’
= protected
Only partial address space was
erased due to existing write protect
blocks.
C
Lock/Unlock
command failed
R2
E X
‘
0
’
= no error
‘
1
’
= error
Sequence or password error during
card lock/unlock operation
C
Card is locked
R2
DataErr
S X
‘
0
’
= card is not
locked
‘
1
’
= card is locked
Card is locked by password.
A
Erase reset
R1 R2
S R
‘
0
’
= cleared
‘
1
’
= set
An erase sequence was cleared
before executing because an output
of erase sequence command was
received.
C
In Idle state
R1 R2
S R
‘
0
’
= card is ready
‘
1
’
= card is in Idle
state
The card enters the Idle state after
power up or reset command. It will
exit this state and become ready upon
completion of this initialization
procedures.
A
CSD overwrite
R2
E X
‘
0
’
= no error
‘
1
’
= error
The host is trying to change the ROM
section, or is trying to reverse the
copy bit (set as original) or permanent
WP bit (unprotected) or he CSD
register.
C