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參數(shù)資料
| 型號(hào)： | HC1-55564-5 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Continuously Variable Slope Delta-Modulator (CVSD) |
| 中文描述： | CVSD, CVSD CODEC, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大小： | 69K |
| 代理商： | HC1-55564-5 |
3
HC-55564
Functional Diagram
(DIP Pin Numbers Shown)
Pin Descriptions
PIN NUMBER
14 LEAD DIP
SYMBOL
DESCRIPTION
1
V
DD
Positive Supply Voltage. Voltage range is 4.5V to 6.0V.
2
Analog GND
Analog Ground connection to D/A ladders and comparator.
3
A
OUT
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 150k
source with DC offset of V
DD
/2. Within
±
2dB of Audio Input. Should be ex-
ternally AC coupled.
4
AGC
Automatic Gain Control output. A logic low level will appear at this output when the recovered
signal excursion reaches one-half of full scale value. In each half cycle full scale is V
DD
/2. The
mark-space ratio is proportional to the average signal level.
5
A
IN
Audio Input to comparator. Should be externally AC coupled. Presents approximately 280k
in
series with V
DD
/2.
6, 7
NC
No internal connection is made to these pins.
8
Digital GND
Logic ground. 0V reference for all logic inputs and outputs.
9
Clock
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such
that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked
out on the negative going clock transition. The clock rate equals the data rate.
10
Encode/
Decode
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the
logic level applied to this input. A low level selects the encode mode, a high level the decode mode.
11
APT
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, how-
ever; internally the CVSD is still functional and a signal is still available at the A
OUT
port. Active low.
12
Digital In
Input for the received digital NRZ data.
13
FZ
Force Zero input. Activating this input resets the internal logic and forces the digital output and the
recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the
digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mV
P-P
inaudible
signal appears at audio output. Active low.
14
Digital Out
Output for transmitted digital NRZ data.
NOTE:
14. No active input should be left in a “floating condition.”
3 BIT
SHIFT
REGISTER
STEP
SIZE
LOGIC
SYLLABIC
FILTER
4ms
DIGITAL
MODULATOR
±
1
SIGNAL
ESTIMATE
FILTER 1msec
10 BIT
DAC
APT
(14)
DIGITAL
OUT
F/F
RESET
6
Z
OUT
10
D
T
RESET
10 BIT
DAC
10
(3) A
OUT
(SIDE TONE)
(4) AGC OUT
Q
RESET
FORCE
ZERO
(9)
DIGITAL
GND
(10)
ENC/DEC
(11) (13)
CLOCK
(8)
(12)
DIGITAL
IN
(1)
V
DD
3V TO 6V
Z
IN
ANALOG
GND
(2)
(5)
A
IN
V
DD
2
COMPARATOR
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| HC1-55564-9 | Voltage Regulator IC; Output Current:1A; Output Voltage Max:125.8V; Output Voltage Min:124.2V |
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相關(guān)代理商/技術(shù)參數(shù) |
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| HC1-55564-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF Modulator |
| HC1-55564-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF Modulator |
| HC1-55564-9 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Continuously Variable Slope Delta-Modulator (CVSD) |
| HC1-5570 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HC157 | 制造商:Texas Instruments 功能描述: |
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