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| 型號(hào)： | HC55143 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Power Universal SLIC Family |
| 中文描述： | 低功耗通用用戶接口家庭 |
| 文件頁(yè)數(shù)： | 12/35頁(yè) |
| 文件大?。?/td> | 382K |
| 代理商： | HC55143 |
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4-12
Notes
2. Overload Level (Two-Wire Port, Off Hook) -
The overload
level is specified at the 2-wire port (V
TR
) with the signal source at
the 4-wire receive port (E
RX
). R
L
= 600
, I
DCMET
≥
18mA.
Increase the amplitude of E
RX
until 1% THD is measured at V
TR
.
Reference Figure 1.
3. Overload Level (Two-Wire Port, On Hook) -
The overload
level is specified at the 2-wire port (V
TR
) with the signal source at
the 4-wire receive port (E
RX
). R
L
=
∞
, I
DCMET
= 0mA. Increase
the amplitude of E
RX
until 1% THD is measured at V
TR
.
Reference Figure 1.
4. LongitudinalImpedance -
The longitudinal impedance is
computed using the following equations, where TIP and RING
voltages are referenced to ground. L
ZT
, L
ZR
, V
T
, V
R
, A
R
and A
T
are defined in Figure 2.
(TIP) L
ZT
= V
T
/A
T
(RING) L
ZR
= V
R
/A
R
where: E
L
= 1V
RMS
(0Hz to 100Hz)
5. LongitudinalCurrentLimit(On-HookActive) -
On-Hook
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E
L
(Figure 3A) until the 2-wire longitudinal current
is greater than 28mA
RMS
/Wire. Under this condition, SHD pin
remains low (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB
2-4
= 20log VTX/E
L
).
6. LongitudinalCurrentLimit(Off-HookActive) -
Off-Hook
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E
L
(Figure 3B) until the 2-wire longitudinal current
is greater than 28mA
RMS
/Wire. Under this condition, SHD pin
remains high (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB
2-4
= 20log VTX/E
L
).
7. LongitudinaltoMetallicBalance -
The longitudinal to
metallic balance is computed using the following equation:
BLME = 20 log (E
L
/V
TR
), where: E
L
and V
TR
are defined in
Figure 4.
8. Metallic to Longitudinal FCC Part 68, Para 68.310 -
The
metallic to longitudinal balance is defined in this spec.
9. LongitudinaltoFour-WireBalance -
Thelongitudinalto4-wire
balance is computed using the following equation:
BLFE = 20 log (E
L
/V
TX
), E
L
and V
TX
are defined in Figure 4.
10. MetallictoLongitudinalBalance -
The metallic to longitudinal
balance is computed using the following equation:
BMLE = 20 log (E
TR
/V
L
), E
RX
= 0
where: E
TR,
V
L
and E
RX
are defined in Figure 5.
11. Four-WiretoLongitudinalBalance -
The4-wiretolongitudinal
balance is computed using the following equation:
BFLE = 20 log (E
RX
/V
L
), E
TR
= source is removed.
where: E
RX,
V
L
and E
TR
are defined in Figure 5.
12. Two-WireReturnLoss -
The 2-wire return loss is computed
using the following equation:
r = -20 log (2V
M
/V
S
) where: Z
D
= The desired impedance; e.g.,
the characteristic impedance of the line, nominally 600
.
(Reference Figure 6).
13. OverloadLevel(4-WirePortOff-Hook) -
The overload level
is specified at the 4-wire transmit port (V
TX
) with the signal
source (E
G
) at the 2-wire port, Z
L
= 20k
,
R
L
= 600
(Reference Figure 7). Increase the amplitude of E
G
until 1%
THD is measured at V
TX
. Note the PTG pin is open, and the
gain from the 2-wire port to the 4-wire port is equal to 1.
14. OverloadLevel(4-WirePortOn-Hook) -
Theoverloadlevelis
specified at the 4-wire transmit port (V
TX
) with the signal source
(E
G
) at the 2-wire port, Z
L
= 20k
,
R
L
=
∞
(Reference Figure 7).
Increase the amplitude of E
G
until 1% THD is measured at V
TX
.
Note the PTG pin is open, and the gain from the 2-wire port to
the 4-wire port is equal to 1.
15. OutputOffsetVoltage -
The output offset voltage is specified
with the following conditions: E
G
= 0, R
L
= 600
, Z
L
=
∞
and is
measured at V
TX
. E
G
, R
L
, V
TX
and Z
L
are defined in Figure 7.
16. Two-WiretoFour-WireFrequencyResponse -
The 2-wire to
4-wire frequency response is measured with respect to
E
G
= 0dBm at 1.0kHz, E
RX
= 0V (VRX input floating), R
L
= 600
.
The frequency response is computed using the following equation:
F
2-4
= 20 log (V
TX
/V
TR
), vary frequency from 300Hz to 3.4kHz
and compare to 1kHz reading.
V
TX
, V
TR
, R
L
and E
G
are defined in Figure 8.
17. Four-WiretoTwo-WireFrequencyResponse -
The 4-wire to 2-
wire frequency response is measured with respect to E
RX
= 0dBm
at 1.0kHz, E
G
source removed from circuit, R
L
= 600
. The
frequency response is computed using the following equation:
F
4-2
= 20 log (V
TR
/E
RX
), vary frequency from 300Hz to 3.4kHz
and compare to 1kHz reading.
V
TR
, R
L
and E
RX
are defined in Figure 8.
18. Four-WiretoFour-WireFrequencyResponse -
The 4-wire
to 4-wire frequency response is measured with respect to
E
RX
= 0dBm at 1.0kHz, E
G
source removed from circuit,
R
L
= 600
. The frequency response is computed using the
following equation:
F
4-4
= 20 log (V
TX
/E
RX
), vary frequency from 300Hz to 3.4kHz
and compare to 1kHz reading.
V
TX ,
R
L
and E
RX
are defined in Figure 8.
19. Two-WiretoFour-WireInsertionLoss(PTG=Open) -
The
2-wire to 4-wire insertion loss is measured with respect to
E
G
= 0dBm at 1.0kHz input signal, E
RX
= 0 (VRX input floating),
R
L
= 600
and is computed using the following equation:
L
2-4
= 20 log (V
TX
/V
TR
)
where: V
TX
, V
TR
, R
L
and E
G
are defined in Figure 8. (Note:
The fuse resistors, R
F
, impact the insertion loss. The specified
insertion loss is for R
F1
= R
F2
= 0).
20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) -
The
2-wire to 4-wire insertion loss is measured with respect to E
G
=
0dBm at 1.0kHz input signal, E
RX
= 0 (VRX input floating), R
L
=
600
and is computed using the following equation:
L
2-4
= 20 log (V
TX
/V
TR
)
where: V
TX
, V
TR
, R
L
and E
G
are defined in Figure 8. (Note:
The fuse resistors, R
F
, impact the insertion loss. The specified
insertion loss is for R
F1
= R
F2
= 0).
21. Four-WiretoTwo-WireInsertionLoss -
The 4-wire to 2-wire
insertion loss is measured based upon E
RX
= 0dBm, 1.0kHz
input signal, E
G
source removed from circuit, R
L
= 600
and is
computed using the following equation:
L
4-2
= 20 log (V
TR
/E
RX
)
where: V
TR
, R
L
and E
RX
are defined in Figure 8.
22. Two-WiretoFour-WireGainTracking -
The 2-wire to 4-wire
gain tracking is referenced to measurements taken for
E
G
= -10dBm, 1.0kHz signal, E
RX
= 0 (VRX output floating),
R
L
= 600
and is computed using the following equation.
G
2-4
= 20
log (V
TX
/V
TR
) vary amplitude -40dBm to +3dBm, or
-55dBm to -40dBm and compare to -10dBm reading.
V
TX
, R
L
and V
TR
are defined in Figure 8.
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
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| HC55143IM | Low Power Universal SLIC Family |
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相關(guān)代理商/技術(shù)參數(shù) |
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| HC55143IM | 功能描述:IC SLIC UNIVERSAL LP 32-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:UniSLIC14 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| HC5514X | 制造商:Harris Corporation 功能描述: |
| HC5514XB | 制造商:Harris Corporation 功能描述: |
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