
HD404889/HD404899/HD404878/HD404868 Series
72
R Port
The R port consists of 34 I/O pins (31 I/O pins in the HD404868 Series) that are addressed in 4-bit units.
Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and
LRB instructions. Output data is stored in the port data register (PDR) for each pin.
The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR8: $034 to
$03C). The DCR registers are mapped onto memory addresses (figure 27).
Ports R0
0
to R0
3
are multiplexed as wakeup input pins
WU
0
to
WU
3
, respectively. Setting of these pins as
peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 29).
Ports R1
0
and R1
1
are multiplexed as peripheral function pins EVNB and EVND, respectively. Setting of
these pins as peripheral function pins is performed by bits 0 and 1 (PMR20, PMR21) of port mode register
2 (PMR2: $00A) (figure 30).
Ports R1
2
to R1
3
and R2
0
are multiplexed as peripheral function pins BUZZ, TOB, and TOC, respectively.
Setting of these pins as peripheral function pins is performed by bits 2 and 3 (PMR22, PMR23) of port
mode register 2 (PMR2: $00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 30 and
31).
Ports R2
1
and R2
2
are multiplexed as peripheral function pins
SCK
and SI/SO, respectively. Setting of
these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register
3 (PMR3: $00B) (figure 31).
Ports R3 to R6 are multiplexed as peripheral function pins SEG1 to SEG16, respectively. Setting of these
pins as segment pins is performed every 4 pins in 4-bit units by port mode register 4 (PMR4: $00C) (figure
32).
Ports R7
0
to R7
3
and R8
0
to R8
1
also function as peripheral function pins AN
0
to AN
5
(HD404889,
HD404899, and HD404868 series only). Peripheral function pin setting of these pins is performed using
bits 1 to 3 (AMR
1
to AMR
3
) of the A/D mode register (AMR :$028). (See Figure 74 in A/D Converter.)