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參數(shù)資料
| 型號： | HCMOS |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Small Signal Bipolar Transistor; Collector Emitter Voltage, Vceo:100V; Transistor Polarity:N Channel; C-E Breakdown Voltage:100V; DC Current Gain Min (hfe):30; Package/Case:R245; Collector Base Voltage:120V |
| 中文描述： | HCMOS家庭特征 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 87K |
| 代理商： | HCMOS |
March 1988
18
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC switching parameters
f
i
Input frequency; for combinatorial logic devices
the maximum number of inputs and outputs
switching in accordance with the device
function table. For sequential logic devices the
clock frequency using alternate HIGH and LOW
for data input or using the toggle mode,
whichever is applicable.
Output frequency; each output.
Maximum clock frequency; clock input
waveforms should have a 50% duty factor and
be such as to cause the outputs to be switching
from 10%V
CC
to 90%V
CC
in accordance with
the device function table.
Hold time; the interval immediately following the
active transition of the timing pulse (usually the
clock pulse) or following the transition of the
control input to its latching level, during which
interval the data to be recognized must be
maintained at the input to ensure their
continued recognition. A negative hold time
indicates that the correct logic level may be
released prior to the timing pulse and still be
recognized.
Clock input rise and fall times; 10% and 90%
values.
Propagation delay; the time between the
specified reference points, normally the 50%
points for 74HC and 74HCU devices on the
input and output waveforms and the 1.3 V
points for the 74HCT devices, with the output
changing from the defined HIGH level to the
defined LOW level.
Propagation delay; the time between the
specified reference points, normally the 50%
points for 74HC and 74HCU devices on the
input and output waveforms and the 1.3 V point
for the 74HCT devices, with the output
changing from the defined LOW level to the
defined HIGH level.
3-state output disable time; the time between
the specified reference points, normally the
50% points for the 74HC and 74HCU devices
and the 1.3 V points for the 74HCT devices on
the output enable input voltage waveform and a
point representing 10% of the output swing on
the output voltage waveform of a 3-state
device, with the output changing from
a HIGH level (V
OH
) to a high impedance
OFF-state (Z).
f
o
f
max
t
h
t
r
,
t
f
t
PHL
t
PLH
t
PHZ
t
PLZ
3-state output disable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and the 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and a point
representing 10% of the output swing on the
output voltage waveform of a 3-state
device, with the output changing from a LOW
level (V
OL
) to a high impedance OFF-state (Z).
3-state output enable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and the 50%
point on the output voltage waveform of a
3-state device, with the output changing from a
high impedance OFF-state (Z) to a HIGH level
(V
OH
).
3-state output enable time; the time between
the specified reference points, normally the
50% points for the 74HC devices and the 1.3 V
points for the 74HCT devices on the output
enable input voltage waveform and the 50%
point on the output voltage waveform of a
3-state device, with the output changing from a
high impedance OFF-state (Z) to a LOW level
(V
OL
).
Removal time; the time between the end of an
overriding asynchronous input, typically a clear
or reset input, and the earliest permissible
beginning of a synchronous control input,
typically a clock input, normally measured at
the 50% points for 74HC devices and the 1.3 V
points for the 74HCT devices on both input
voltage waveforms.
Set-up time; the interval immediately preceding
the active transition of the timing pulse (usually
the clock pulse) or preceding the transition of
the control input to its latching level, during
which interval the data to be recognized must
be maintained at the input to ensure their
recognition. A negative set-up time indicates
that the correct logic level may be initiated
sometime after the active transition of the
timing pulse and still be recognized.
t
PZH
t
PZL
t
rem
t
su
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