參數(shù)資料
型號: HCMS-2965
英文描述: Bipolar Transistor; Collector Emitter Voltage, Vceo:350V; Transistor Polarity:NPN; Power Dissipation:1W; DC Current Gain Min (hfe):40; Collector Current:1A; Package/Case:3-TO-39; DC Current Gain Max (hfe):60; Terminal Type:5
中文描述: 高性能CMOS 5 × 7字母數(shù)字顯示器
文件頁數(shù): 7/16頁
文件大小: 138K
代理商: HCMS-2965
7
AC Timing Characteristics Over Temperature Range (-40
°
C to +85
°
C)
Timing
Diagram
Ref.
Number
4.5 V < V
LOGIC
<5.5 V
Symbol
Min.
V
LOGIC
= 3 V
Min.
Description
Max.
Max.
Units
1
Register Select Setup Time to
Chip Enable
t
rss
10
10
ns
2
Register Select Hold Time to
Chip Enable
t
rsh
10
10
ns
3
Rising Clock Edge to Falling
Chip Enable Edge
t
clkce
20
20
ns
4
Chip Enable Setup Time to
Rising Clock Edge
t
ces
35
55
ns
5
Chip Enable Hold Time to
Rising Clock Edge
t
ceh
20
20
ns
6
Data Setup Time to Rising
Clock Edge
t
ds
10
10
ns
7
Data Hold Time after Rising
Clock Edge
t
dh
10
10
ns
8
Rising Clock Edge to D
OUT[1]
Propagation Delay D
IN
to D
OUT
Simultaneous Mode for
one IC
[1,2]
t
dout
t
doutp
10
40
10
65
ns
9
18
30
ns
10
CE Falling Edge to D
OUT
Valid
Clock High Time
t
cedo
t
clkh
t
clkl
t
rstl
F
cyc
F
inosc
25
45
ns
11
80
100
ns
12
Clock Low Time
80
100
ns
Reset Low Time
50
50
ns
Clock Frequency
5
4
MHz
Internal Display Oscillator
Frequency
80
210
80
210
KHz
Internal Refresh Frequency
F
rf
F
exosc
150
410
150
400
Hz
External Display Oscillator
Frequency
Prescaler = 1
Prescaler = 8
51.2
410
1000
8000
51.2
410
1000
8000
KHz
KHz
Notes:
1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.
2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
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