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參數(shù)資料
| 型號： | HCPL7100 |
| 英文描述： | HEATSHRINK FABRIC 1.18X200' |
| 中文描述： | 高速CMOS光耦合器 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 240K |
| 代理商： | HCPL7100 |
1-410
Notes:
1. The LED is OFF when the V
is high and ON when V
is low.
2. Device considered a two terminal device; pins 1-4 shorted together and pins 5-8 shorted together.
3. In accordance with UL 1577, for devices with minimum V
specified at 3750 V rms, each optocoupler is proof-tested by applying an
insulation test voltage greater than 4500 V rms for one second (leakage current detection limit I
< 5
μ
A). This test is performed
before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table.
4. C
I
is the capacitance measured at pin 2 (V
).
5. t
PHL
propagation delay is measured from the 50% level on the falling edge of the V
I
signal to the logic switching level of the V
O
signal.
t
PLH
propagation delay is measured from the 50% level on the rising edge of the V
I
signal to the logic switching level of the V
O
signal.
6. The logic switching levels are 1.5 V for TTL signals (0-3 V) and 2.5 V for CMOS signals (0-5 V).
7. PWD is defined as |t
PHL
- t
PLH
|. %PWD (percent pulse width distortion) is equal to PWD in ns divided by symbol duration (bit length)
in ns.
8. Minimum data rate is calculated as follows: %PWD/PWD where %PWD is typically chosen by the design engineer (30% is common).
9. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at the same temperature, supply voltage,
and output load within the recommended operating condition range.
10. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
O
> 3.2 V. CM
L
is the maximum
common mode voltage slew rate that can be sustained while maintaining V
O
< 0.8 V. The common mode voltage slew rates apply to
both rising and falling common mode voltage edges.
11. Unloaded dynamic power dissipation is calculated as follows: C
PD
V
DD2
f + I
DD
V
DD
where f is switching frequency in MHz.
Figure 1. Recommended Application Circuit.
Figure 2. Recommended Printed Circuit Board Layout.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCPL-7100#300 | 制造商:Hewlett Packard Co 功能描述: |
| HCPL7101300 | 制造商:Hewlett Packard Co 功能描述: |
| HCPL-7510 | 功能描述:隔離放大器 4.5 - 5.5 SV +/-3% RoHS:否 制造商:Texas Instruments 輸入補償電壓:1.5 mV 共模抑制比（最小值）:95 dB 帶寬:60 KHz 工作電源電壓:3.3 V 電源電流:8 mA 工作溫度范圍:- 40 C to + 105 C 安裝風格:SMD/SMT 封裝 / 箱體:SOP-8 封裝:Tube |
| HCPL-7510/EVAL | 制造商:Avago Technologies 功能描述: |
| HCPL-7510-000E | 功能描述:隔離放大器 4.5 - 5.5 SV +/-3% RoHS:否 制造商:Texas Instruments 輸入補償電壓:1.5 mV 共模抑制比（最小值）:95 dB 帶寬:60 KHz 工作電源電壓:3.3 V 電源電流:8 mA 工作溫度范圍:- 40 C to + 105 C 安裝風格:SMD/SMT 封裝 / 箱體:SOP-8 封裝:Tube |
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