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參數(shù)資料
| 型號： | HCS112DMSR |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened Dual JK Flip-Flop |
| 中文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 180K |
| 代理商： | HCS112DMSR |
11
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS112DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCS112KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCS112D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCS112K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCS112HMSR
+25
o
C
Die
Die
HCS112MS
Radiation Hardened
Dual JK Flip-Flop
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CP1
KA
JA
SA
QA
QA
GND
QB
VCC
RB
CPB
KB
JB
SB
QB
RA
CP1
KA
JA
SA
QA
QA
QB
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VCC
RA
RB
CPB
KB
JB
SB
QB
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The output changes state on the
negative going transition of the clock pulse. Set and reset
are accomplished asynchronously by a logic low input level.
The HCS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518830
File Number
3558.1
D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCS112K | Radiation Hardened Dual JK Flip-Flop |
| HCS112HMSR | Radiation Hardened Dual JK Flip-Flop |
| HCS125 | Radiation Hardened Quad Buffer, Three-State |
| HCS125KMSR | Radiation Hardened Quad Buffer, Three-State |
| HCS125MS | Radiation Hardened Quad Buffer, Three-State(抗輻射四緩沖器（三態(tài)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCS112HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCS112K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCS112KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCS112MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCS114-01GG | 制造商:Advanced Interconnect 功能描述: |
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