參數(shù)資料
型號(hào)： HCS120
廠商： Microchip Technology Inc.
英文描述： Bi-directional Authenticator(雙向文電鑒別碼)
中文描述： 雙向認(rèn)證者（雙向文電鑒別碼）
文件頁數(shù)： 70/170頁
文件大?。?/td> 4191K
代理商： HCS120
PIC16F62X
DS40300C-page 68
Preliminary
2003 Microchip Technology Inc.
REGISTER 12-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN
:
Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set)
1
= Serial port enabled
0
= Serial port disabled
bit 6
RX9
: 9-bit Receive Enable bit
1
= Selects 9-bit reception
0
= Selects 8-bit reception
bit 5
SREN
: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1
= Enables single receive
0
= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4
CREN
: Continuous Receive Enable bit
Asynchronous mode:
1
= Enables continuous receive
0
= Disables continuous receive
Synchronous mode:
1
= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0
= Disables continuous receive
bit 3
ADEN:
Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1
= Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set
0
= Disables address detection, all bytes are received, and ninth bit can be used as PARITY bit
Asynchronous mode 8-bit (RX9=0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2
FERR
: Framing Error bit
1
= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0
= No framing error
bit 1
OERR
: Overrun Error bit
1
= Overrun error (Can be cleared by clearing bit CREN)
0
= No overrun error
bit 0
RX9D
:
9th bit of received data (Can be PARITY bit)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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