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參數資料
| 型號： | HCS160K |
| 廠商： | Intersil Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened BCD Decade Synchronous Counter |
| 中文描述： | 輻射加固BCD碼十年同步計數器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 120K |
| 代理商： | HCS160K |
183
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS160DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCS160KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCS160D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCS160K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCS160HMSR
+25
o
C
Die
Die
HCS160MS
Radiation Hardened
BCD Decade Synchronous Counter
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
MR
CP
P0
P1
P2
P3
GND
PE
VCC
Q0
Q1
Q2
Q3
TE
SPE
TC
MR
CP
P0
P1
P2
P3
PE
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset: >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
-Standard Outputs: 10 LSTTL Loads
-Bus Driver Outputs: 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
-VIL = 30% of VCC Max
-VIH = 70% of VCC Min
Input Current Levels Ii
≤
5
μ
A @ VOL, VOH
Description
The Intersil HCS160MS is a Radiation Hardened high speed
presettable BCD decade synchronous counter that features an
asynchronous reset and look-ahead carry logic. Counting and
parallel presetting are accomplished synchronously with the low-
to-high transition of the clock. A low level on the synchronous
parallel enable input, SPE, disables counting and allows data at
the preset inputs, P0 - P3, to be loaded into the counter. The
counter is reset by a low on the master reset input, MR. Two count
enables, PE and TE are provided for n-bit cascading. TE also
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to
enable the next cascaded stage to count.
The HCS160MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS160MS is supplied in a 16 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix.)
September 1995
Spec Number
518834
File Number
2296.2
D
相關PDF資料 |
PDF描述 |
|---|---|
| HCS160KMSR | Radiation Hardened BCD Decade Synchronous Counter |
| HCS160MS | Radiation Hardened BCD Decade Synchronous Counter |
| HCS163KMSR | Radiation Hardened Synchronous Presettable Counter |
| HCS163MS | Radiation Hardened Synchronous Presettable Counter |
| HCS163DMSR | Radiation Hardened Synchronous Presettable Counter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCS160KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened BCD Decade Synchronous Counter |
| HCS160MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened BCD Decade Synchronous Counter |
| HCS161D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Synchronous Counter |
| HCS161DMSR | 制造商:Intersil Corporation 功能描述:COUNTER SGL 4BIT BINARY UP 16PIN SBDIP - Rail/Tube |
| HCS161HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Synchronous Counter |
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