參數(shù)資料
型號： HCS473IPQTP
廠商： Microchip Technology Inc.
英文描述： Code Hopping Encoder and Transponder
中文描述： 跳碼編碼器和轉(zhuǎn)發(fā)器
文件頁數(shù)： 17/68頁
文件大?。?/td> 1629K
代理商： HCS473IPQTP
2002 Microchip Technology Inc.
Preliminary
DS40035C-page 15
HCS473
FIGURE 3-5:
QUE COUNTER TIMING DIAGRAM
3.1.4.5
Counter Select (CNTSEL)
The counter select option selects between a 16-bit or
20-bit counter. This option changes the way the 32-bit
hopping portion is constructed, as indicated in
Figure 3-2. The 16-bit counter format additionally
includes two overflow bits for increasing the synchroni-
zation counter range, see Section 3.1.7.
CNTSEL options:
16-bit synchronization counter
20-bit synchronization counter
3.1.4.6
Low Voltage Trip Point Select
(VLOWSEL)
The HCS473’s battery voltage detector detects when
the supply voltage drops below a predetermined value.
The value is selected by the Low Voltage Trip Point
Select (VLOWSEL) configuration option (Table 3-6).
VLOWSEL options:
2.2V trip point
3.3V trip point
The low voltage detector result (VLOW) is included in
Hopping code transmissions allowing the receiver to
indicate when the transmitter battery is low (Figure 3-
2). The HCS473 also indicates a low battery condition
by changing the LED operation (Section 3.1.5).
The HCS473 samples the internal low voltage detector
at the end of each code word’s first preamble bit. The
transmitted VLOW status will be a ‘0’ as long as the low
voltage detector indicates V
DD
is above the selected
low voltage trip point. VLOW will change to a ‘1’ if V
DD
drops below the selected low voltage trip point.
TABLE 3-1:
VLOW STATUS BIT
3.1.4.7
PLL Interface Select (PLLSEL)
The S3/RFEN pin may be configured as an RF enable
output to an RF PLL. The pin’s behavior is coordinated
with the DATA pin to activate a typical PLL in either
ASK or FSK mode.
The PLL Interface (PLLSEL) configuration option con-
trols the output as shown for Encoder operation in
Figure 3-6. Please refer to Section 3.2.8 for RFEN
behavior during LF communication.
PLLSEL options:
ASK PLL Setup
FSK PLL Setup
3.1.4.8
RF Enable Output (RFEN)
The S3/RFEN pin of the HCS473 can be configured to
function as an RF enable output signal. When enabled,
the pin is driven high whenever data is transmitted
through the DATA pin; the S3/RFEN pin can therefore
not be used as an input in this configuration. The RF
enable option bit functions in conjunction with the PLL
interface select option, PLLSEL.
RFEN options:
S3/RFEN pin functions as S3 switch input only
S3/RFEN pin functions as RFEN output only
t
≥
T
DB
Button Input
Sx
Code Words
Transmitted
T
DB
≤
t
≤
T
QUE
QUE1:0 = 00
2
Synch CNT = X
Transmission:
QUE1:0 = 01
2
Synch CNT = X+1
Transmission:
T
DB
1st Button Press
All Buttons Released
2nd Button Press
VLOW
Description
0
V
DD
is above selected trip voltage
V
DD
is below selected trip voltage
1
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