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參數(shù)資料
| 型號(hào)： | HCS573MS |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Low-Voltage, Dual Hot-Swap Controllers with Independent On/Off Control |
| 中文描述： | 輻射加固八路透明鎖存器，三態(tài) |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 144K |
| 代理商： | HCS573MS |
324
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS573DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead SBDIP
HCS573KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
HCS573D/Sample
+25
o
C
Sample
20 Lead SBDIP
HCS573K/Sample
+25
o
C
Sample
20 Lead Ceramic Flatpack
HCS573HMSR
+25
o
C
Die
Die
HCS573MS
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20, LEAD FINISH C
TOP VIEW
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20, LEAD FINISH C
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
LE
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCS573MS is a Radiation Hardened octal transpar-
ent three-state latch with an active low output enable. The
HCS573MS utilizes advanced CMOS/SOS technology. The
outputs are transparent to the inputs when the Latch Enable (LE)
is HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the tri-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCS573MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS573MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518771
File Number
4056
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCS573HMSR | Radiation Hardened Octal Transparent Latch, Three-State |
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| HCS74DMSR | Low-Voltage, Dual Hot-Swap Controllers with Independent On/Off Control |
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