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參數(shù)資料
| 型號： | HCTL-2032-SC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quadrature Decoder/Counter Interface ICs |
| 中文描述： | 正交解碼器/計數(shù)器接口芯片 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 302K |
| 代理商： | HCTL-2032-SC |
16
Cascade Considerations
(HCTL-2032 / 2032-SC only)
The HCTL-2032 / 2032-SC 's
cascading system allows for
position reads of more than
four bytes. These reads can be
accomplished by latching all the
bytes and then reading the
bytes sequentially over the 8-bit
bus. It is assumed here that,
externally, a counter followed by
a latch is used to count any
count that exceeds 32 bits. This
configuration is compatible with
the HCTL-2032 / 2032-SC
internal counter/latch
combination.
Consider the sequence of events
for a read cycle that starts as
the HCTL-2032 / 2032-SC 's
internal counter rolls over. On
the rising clock edge, count data
is updated in the internal
counter, rolling it over. A count-
cascade pulse (CNT
CAS
) will be
generated with some delay after
the rising clock edge (t
CHD
).
There will be additional
propagation delays through the
external counters and registers.
Meanwhile, with SEL and OE
low to start the read, the
internal latches are inhibited at
the falling edge and do not
update again till the inhibit is
reset.
If the CNT
CAS
pulse now toggles
the external counter and this
count gets latched a major
count error will occur. The
count error is because the
external latches get updated
when the internal latch is
inhibited.
Valid data can be ensured by
latching the external counter
data when the high byte read is
started (SEL and OE low). This
latched external byte
corresponds to the count in the
inhibited internal latch. The
cascade pulse that occurs
during the clock cycle when the
read begins gets counted by the
external counter and is not lost.
For example, suppose the
HCTL-2032 / 2032-SC count is
at FFFFFFFFh and an external
counter is at F0h, with the
count going up. A count
occurring in the HCTL-2032 /
2032-SC will cause the counter
to roll over and a cascade pulse
will be generated. A read
starting on this clock cycle will
show FFFFFFFFh from the
HCTL-2032 / 2032-SC. The
external latch should read F0h,
but if the host latches the count
after the cascade signal
propagates through, the external
latch will read F1h.
Figure 16. Decode and Cascade Output Diagram (4x)
FFFFFFFDh
FFFFFFFEh
FFFFFFFh
00000000h
FFFFFFFEh
FFFFFFFh
COUNT
CNT cas
CNT DCDR
U/Dbar
CHB FLT
CHA FLT
CLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HCTL-2032-SCT | 制造商:Avago Technologies 功能描述:QUADRATURE DECODER/ COUNTER INTRFC IC 32PIN - Tape and Reel |
| HCT-L-R5A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HCT-L-R5B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HCT-L-R-HA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HCT-L-R-HB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
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