- 您現(xiàn)在的位置：買賣IC網 > PDF目錄371785 > HCTS109MS (Intersil Corporation) Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 PDF資料下載
參數(shù)資料
| 型號： | HCTS109MS |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 |
| 中文描述： | 輻射加固雙JK觸發(fā)器拖鞋 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 170K |
| 代理商： | HCTS109MS |
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS109DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCTS109KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCTS109D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCTS109K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCTS109HMSR
+25
o
C
Die
Die
HCTS109MS
Radiation Hardened
Dual JK Flip Flop
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
RI
J1
K1
CP1
S1
Q1
GND
Q1
VCC
J2
K2
CP2
S2
Q2
Q2
R2
R1
J1
K1
CP1
S1
Q1
Q1
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VCC
R2
J2
K2
CP2
S2
Q2
Q2
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Logic Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS109MS is a Radiation Hardened Dual JK
Flip Flop with set and reset. The flip flop changes state with
the positive transition of the clock (CP1 or CP2).
The HCTS109MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS109MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518601
File Number
2141.2
相關PDF資料 |
PDF描述 |
|---|---|
| HCTS109T | Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CFP -55 to 125 |
| HCTS109D | Radiation Hardened Dual JK Flip Flop |
| HCTS109K | Radiation Hardened Dual JK Flip Flop |
| HCTS109KTR | Radiation Hardened Dual JK Flip Flop |
| HCTS132HMSR | Radiation Hardened Quad 2-Input NAND Schmitt Trigger |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS109T | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip Flop |
| HCTS10D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input NAND Gate |
發(fā)布緊急采購，3分鐘左右您將得到回復。