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參數(shù)資料
| 型號： | HD-4702 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Programmable Bit Rate Generator(CMOS 可編程位速率發(fā)生器) |
| 中文描述： | CMOS可編程比特率發(fā)生器（的CMOS可編程位速率發(fā)生器） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 41K |
| 代理商： | HD-4702 |
5-1
March 1997
HD-4702
CMOS Programmable Bit Rate Generator
Features
HD-4702 Provides 13 Commonly Used Bit Rates
Uses a 2.4576MHz Crystal/Input for Standard
Frequency Output (16 Times Bit Rate)
Low Power Dissipation
Conforms to EIA RS-404
One HD-4702 Controls up to Eight Transmission
Channels
Initialization Circuit Facilitates Diagnostic Fault
Isolation
On-Chip Input Pull-Up Circuit
Description
The HD-4702 Bit Rate Generator provides the necessary clock
signals for digital data transmission systems, such as a UART. It
generates 13 commonly used bit rates using an on-chip crystal
oscillator or an external input. For conventional operation gener-
ating 16 output clock pulses per bit period, the input clock fre-
quency must be 2.4576MHz (i.e. 9600 Baud x 16 x 16, since
there is an internal
÷
16 prescaler). A lower input frequency will
result in a proportionally lower output frequency.
The HD-4702 can provide multi-channel operation with a mini-
mum of external logic by having the clock frequency CO and the
÷
8 prescaler outputs Q0, Q1, Q2 available externally. All signals
have a 50% duty cycle except 1800 Baud, which has less than
0.39% distortion.
The four rate select inputs (S0-S3) select which bit rate is at the
output (Z). See Truth Table for Rate Select Inputs for select code
and output bit rate. Two of the 16 select codes for the HD-4702 do
not select an internally generated frequency, but select an input
into which the user can feed either a different frequency, or a static
level (High or Low) to generate “ZERO BAUD”.
The bit rates most commonly used in modern data terminals
(110, 150, 300, 1200, 2400 Baud) require that no more than one
input be grounded for the HD-4702, which is easily achieved with
a single 5-position switch.
The HD-4702 has an initialization circuit which generates a mas-
ter reset for the scan counter. This signal is derived from a digital
differentiator that senses the first high level on the CP input after
the E
CP
input goes low. When E
CP
is high, selecting the crystal
input, CP must be low. A high level on CP would apply a continu-
ous reset. See Clock Modes and Initialization below.
Truth Table
Pinout
HD-4702 (CERDIP, PDIP)
TOP VIEW
Ordering Information
PACKAGE
TEMP.
RANGE (
o
C)
PART NUMBER
PKG. NO.
PDIP
-40 to +85
HD3-4702-9
E16.3
CERDIP
-40 to +85
HD1-4702-9
F16.3
SMD#
-55 to +125
5962-9051801MEA
F16.3
TRUTH TABLE FOR RATE SELECT INPUTS
(Using 2.4576MHz Crystal)
S2
S1
S3
S0
OUTPUT RATE (Z)
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
MUX Input (IM)
MUX Input (IM)
50 Baud
75 Baud
134.5 Baud
200 Baud
600 Baud
2400 Baud
9600 Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
150 Baud
110 Baud
NOTE: 19200 Baud by connecting Q2 to IM.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q0
Q1
Q2
E
CP
CP
O
X
GND
I
X
V
CC
S0
S1
S2
S3
Z
CO
I
M
File Number
2954.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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