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參數(shù)資料
| 型號(hào)： | HD-6408 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Asynchronous Serial Manchester Adapter (ASMA) |
| 中文描述： | 曼徹斯特的CMOS異步串行適配器（財(cái)產(chǎn)安全管理） |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | HD-6408 |
5-3
Pin Description
PIN
TYPE
SYMBOL
SECTION
DESCRIPTION
1
O
VW
Decoder
Output high indicates receipt of a VALID WORD.
2
O
ESC
Encoder
ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The En-
coder samples SDI on the low-to-high transition of ESC.
3
O
TD
Decoder
TAKE DATA output is high during receipt of data after identification of a sync pulse
and two valid Manchester data bits.
4
O
SDO
Decoder
SERIAL DATA OUT delivers received data in correct NRZ format.
5
I
DC
Decoder
DECODER CLOCK input drives the transition finder, and the synchronizer which
in turn supplies the clock to the balance of the Decoder. Input a frequency equal to
12X the data rate.
6
I
BZI
Decoder
A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative
state. This pin must be held high when the Unipolar input is used.
7
I
BOI
Decoder
A high input should be applied to BIPOLAR ONE IN when the bus is in its positive
state, this pin must be held low when the Unipolar input is used.
8
I
UDI
Decoder
With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition
finder circuit. If not used this input must be held low.
9
O
DSC
Decoder
DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK
÷
12),
synchronized by the recovered serial data stream.
10
O
CDS
Decoder
COMMAND/DATA SYNC output high occurs during output of decoded data which
was preceded by a Command synchronizing character. A low output indicates a
Data synchronizing character.
11
I
DR
Decoder
A high input to DECODER RESET during a rising edge of DECODER SHIFT
CLOCK resets the decoder bit counting logic to a condition ready for a new word.
12
I
GND
Both
GROUND supply pin.
13
I
MR
Both
A high on MASTER RESET clears the 2:1 counters in both the encoder and decod-
er and the
÷
6 counter.
14
O
DBS
Encoder
DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER
CLOCK.
15
O
BZO
Encoder
BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative
sense of a bipolar line driver.
16
I
OI
Encoder
A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.
17
O
BOO
Encoder
BIPOLAR ONE OUT is an active low output designed to drive the one or positive
sense of a bipolar line driver.
18
I
SDI
Encoder
SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER
SHIFT CLOCK.
19
I
EE
Encoder
A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preced-
ing cycle being completed).
20
I
SS
Encoder
SYNC SELECT actuates a Command sync for an input high and data sync for an
input low.
21
O
SD
Encoder
SEND DATA is an active high output which enables the external source of serial
data.
22
I
SCI
Encoder
SEND CLOCK IN is 2X the Encoder data rate.
23
I
EC
Encoder
ENCODER CLOCK is the input to the 6:1 divider.
24
I
V
CC
Both
V
CC
is the +5V power supply pin. A 0.1
μ
F decoupling capacitor from V
CC
(pin 24)
to GND (pin 12) is recommended.
HD-6408
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD14066BG | SPST Analog Switch |
| HD14066BP | SPST Analog Switch |
| HD146818AFP | Real-Time Clock |
| HD146818AP | Real-Time Clock |
| HD146818FP | Real-Time Clock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD-6408_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Asynchronous Serial Manchester Adapter (ASMA) |
| HD6409 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD-6409 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD-6409/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
| HD-6409_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Manchester Encoder-Decoder |
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