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參數(shù)資料
| 型號(hào)： | HD404654S |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-Bit Single-Chip Microcomputer |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 69/109頁 |
| 文件大小： | 430K |
| 代理商： | HD404654S |
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HD404654 Series
69
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode.
In internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.
If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.
Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/ receive data but only
outputs the transmit clock from the
SCK
1
pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
Output Level Control in Idle States:
When serial interface 1 is in STS instruction wait state, the output
of serial output pin SO
1
can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B:
$028) to 0 or 1. The output level control example of serial interface 1 is shown in figure 54. Note that the
output level cannot be controlled in transfer state.
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