參數(shù)資料
型號: HD4074654H
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer
中文描述: 4位單片機
文件頁數(shù): 66/109頁
文件大小: 430K
代理商: HD4074654H
HD404654 Series
66
Table 24 Serial Interface 1 Operating Modes
SM1A
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
1
0
Receive mode
1
Transmit/receive mode
Pin Setting:
The R4
1
/
SCK
1
pin is controlled by writing data to serial mode register 1A (SM1A: $005).
Pins R4
2
/SI
1
and R4
3
/SO
1
are controlled by writing data to port mode register A (PMRA: $004). Refer to
the following section Registers for Serial Interface for details.
Transmit Clock Source Setting:
The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following
section Registers for Serial Interface for details.
Data Setting:
Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L:
$006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data
register 1. The serial data is shifted by the transmit clock and is input from or output to an external system.
The output level of the SO
1
pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.
Transfer Control:
Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000
by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When
the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal
counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t
cyc
to 8192t
cyc
by setting bits 0 to 2 (SM1A0–SM1A2) of serial mode register 1A (SM1A: $005) and bit 0
(SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 25.
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