參數(shù)資料
型號(hào)： HD407A4639R
廠商： Hitachi,Ltd.
英文描述： 4-Bit Single-Chip Microcomputer(4位單片微計(jì)算機(jī))
中文描述： 4位單片機(jī)（4位單片微計(jì)算機(jī)）
文件頁(yè)數(shù)： 8/133頁(yè)
文件大?。?/td> 803K
代理商： HD407A4639R
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
HD404639R Series
8
Compare control register
Compare data register
Compare enable register
TG mode register
TG control register
Data
(464 digits)
V = 1
(bank = 1)
0
$000
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
64
80
608
960
1023
$040
$050
4
5
6
7
8
9
0
3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
10
11
32
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
63
$020
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03F
$00A
$00B
$00E
$00F
W
W
R/W
R/W
W
R/W
R/W
W
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
W
R/W
$090
$25F
58
59
54
55
56
$3C0
$260
RAM-mapped registers
Memory registers (MR)
Not used
Data (464 digits 2)
V = 0 (bank 0)
V = 1 (bank 1)
Data (144 digits)
Stack (64 digits)
Interrupt control bits area
Port mode register A
Serial mode register 1A
Serial data register 1 lower
Serial data register 1 upper
Timer mode register A
Timer mode register B1
Timer B
Miscellaneous register
Timer mode register C1
Timer C
Timer mode register B2
Timer mode register C2
Timer mode register D2
Register flag area
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
Port R9 DCR
Port RA DCR
Port RB DCR
Port RC DCR
Port D to D DCR
Port D to D DCR
Port D to D DCR
Not used
V register
Data
(464 digits)
V = 0
(bank = 0)
The data area has two banks:
bank 0 (V = 0) to bank 1 (V = 1)
10
11
14
15
Timer read register B lower
Timer read register B upper
Timer read register C lower
Timer read register C upper
Timer write register B lower
Timer write register B upper
Timer write register C lower
Timer write register C upper
R:
W:
R/W:
$090
Read only
Write only
Read/Write
Note:
*
$011
$012
W
W
R
R
17
18
Timer read register D lower
Timer read register D upper
Timer write register D lower
Timer write register D upper
144
Timer mode register D1
Timer D
R
W
W
W
27
28
29
30
31
$3FF
Serial mode register 2A
Serial mode register 2B
Serial data register 2 lower
Serial data register 2 upper
W
W
R/W
W
W
W
W
W
W
W
W
60
Port mode register B
Port mode register C
Detection edge select register 1
Detection edge select register 2
Serial mode register 1B
System clock select register 1
System clock select register 2
Not used
Not used
$031
53
Two registers are mapped
on the same area.
Not used
752
$2F0
*
(PMRA)
(SM1A)
(SR1L)
(SR1U)
(TMA)
(TMB1)
(TRBL/TWBL)
(TRBU/TWBU)
(MIS)
(TMC1)
(TRCL/TWCL)
(TRCU/TWCU)
(TMD1)
(TRDL/TWDL)
(TRDU/TWDU)
(TMB2)
(TMC2)
(TMD2)
(CCR)
(CDR)
(CER)
(TGM)
(TGC)
(SM2A)
(SM2B)
(SR2L)
(SR2U)
(PMRB)
(PMRC)
(ESR1)
(ESR2)
(SM1B)
(SSR1)
(SSR2)
(DCD0)
(DCD1)
(DCD2)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(DCR9)
(DCRA)
(DCRB)
(DCRC)
R/W
Not used
57
(TRBL)
(TRBU)
(TRCL)
(TRCU)
(TRDL)
(TRDU)
(TWBL)
(TWBU)
(TWCL)
(TWCU)
(TWDL)
(TWDU)
Figure 2 RAM Memory Map
相關(guān)PDF資料
PDF描述
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