參數(shù)資料
型號: HD40A4638R
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer(4位單片微計算機)
中文描述: 4位單片機(4位單片微計算機)
文件頁數(shù): 85/133頁
文件大?。?/td> 803K
代理商: HD40A4638R
HD404639R Series
85
Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and puts the serial
interface in transfer state. However, note that if continuous clock output mode is selected in internal
clock mode, the serial interface does not enter transfer state but enters continuous clock output state
(17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial
interface 1, and STS wait state is entered.
If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is
set by the octal counter that is reset to 000.
Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the
SCK
1
pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
Output Level Control in Idle States:
When serial interface 1 is in STS instruction wait state and when
serial interface 2 is in SM2A read wait state and transmit clock state, the output of each serial output pin,
SO
1
and SO
2
,
can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or
1, or bit 1 (SM2B1) of serial mode register 2B (SM2B: $01C) to 0 or 1. The output level control example
of serial interface 1 is shown in figure 68. Note that the output level cannot be controlled in transfer state.
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