參數(shù)資料
型號(hào): HD40A4639R
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer(4位單片微計(jì)算機(jī))
中文描述: 4位單片機(jī)(4位單片微計(jì)算機(jī))
文件頁數(shù): 21/133頁
文件大小: 803K
代理商: HD40A4639R
HD404639R Series
21
Interrupt Enable Flag (IE: $000, Bit 0):
Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (
INT
0
,
INT
1
, INT
2
–INT
4
):
Five external interrupt signals.
External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023):
IF0 and IF1 are set at the falling
edge of signals input to
INT
0
and
INT
1
, and IF2–IF4 are set at the rising or falling edge of signals input to
INT
2
–INT
4
, as listed in table 5. The INT
2
–INT
4
interrupt edges are selected by the detection edge select
registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.
Table 5 External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023)
IF0–IF4
Interrupt Request
0
No
1
Yes
Bit
Initial value
Read/Write
Bit name
3
0
W
ESR13
2
0
W
ESR12
0
0
W
ESR10
1
0
W
ESR11
Detection edge selection register 1 (ESR1: $026)
ESR11
0
1
ESR10
0
1
0
1
INT
2
detection edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
ESR13
0
1
ESR12
0
1
0
1
INT
3
detection edge
No detection
Falling-edge detection
Rising-edge detection
Double-edge detection
Note: Both falling and rising edges are detected.
*
*
Figure 12 Detection Edge Selection Register 1 (ESR1)
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