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| 型號： | HD40A4669 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計算機) |
| 中文描述： | 低電壓如同在微機芯片的DTMF產(chǎn)生電路（帶雙音多頻電路的低電壓微計算機） |
| 文件頁數(shù)： | 79/142頁 |
| 文件大小： | 894K |
| 代理商： | HD40A4669 |
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HD404669 Series
79
Serial Interface Operation
Selecting and Changing the Operating Mode:
Table 19 lists the serial interface’s operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial
mode register 1A (SM1A: $005) settings; to change the operating mode, always initialize the serial
interface internally by writing data to serial mode register 1A (SM1A: $005). Note that the serial interface
is initialized by writing data to serial mode register 1A(SM1A: $005). Refer to the following Serial Mode
Register 1A section for details.
Pin Setting:
The R4
1
/
SCK
1
pin is controlled by writing data to serial mode register 1A (SM1A: $005).
The R4
2
/SI
1
and R4
3
/SO
1
pins are controlled by writing data to port mode register A (PMRA: $004). Refer
to the following Registers for Serial Interface section for details.
Transmit Clock Source Setting:
The transmit clock source is set by writing data to serial mode register
1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following Registers for Serial
Interface section for details.
Data Setting:
Transmit data is set by writing data to the serial data register 1 (SR1L: $006, SR1U: $007).
Receive data is obtained by reading the contents of the serial data register 1 (SR1L: $006, SR1U: $007).
The serial data is shifted by the transmit clock and is input from or output to an external system.
The output level of the SO
1
pin is invalid until the first data is output after MCU reset, or until the
High/Low level control in idle states is performed.
Table 19 Serial Interface Operating Modes
SM1A
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Serial clock continuous output mode
1
Transmit mode
1
0
Receive mode
1
Transmit/receive mode
Transfer Control:
The serial interface is activated by the STS instruction. The octal counter is reset to
000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t
cyc
to 8192t
cyc
by setting bits 2 to 0 (SM1A2– SM1A0) of serial mode register 1A (SM1A: $005) and bit 0
(SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 20.
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