
HD404374/HD404384/HD404389/HD404082/HD404084 Series
62
Table 23
Circuit Configurations of I/O Pins (cont)
Type
Circuit Configuration
Pins
SCK
Perip-
heral
function
pins
I/O pins
V
CC
V
CC
MIS3
PDR
I/O control signal
SCK
Pull-up control signal
Output data
Input data
SCK
Output
pins
V
CC
V
CC
MIS3
PDR
SMR22
SO
Pull-up control signal
PMOS control signal
Output data
SO
V
CC
V
CC
MIS3
PDR
Pull-up control signal
Output data
TOB, TOC
TOB, TOC
Input
pins
RESET
Input data
RESET
V
CC
MIS3
PDR
WU
0
etc.
WU
,
INT
0
,
EVNB, SI
A/D Input
A/D channel control signal
AN
4
, AN
5
*
1
Note:
In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state
and peripheral function selections are cleared.
1. Applies to HD404389 Series.