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參數(shù)資料
| 型號： | HD49338F |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | CDS/PGA & 12-bit A/D Converter |
| 中文描述： | 的CDS /美國PGA |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 247K |
| 代理商： | HD49338F |
HD49338F/HF
Rev.1.0, Apr 20, 2004, page 6 of 22
Internal Functions
Functional Description
CDS input
CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period.
Gain can be adjusted using 10 bits of register (0.033 dB steps) within the range from –2.36 dB to 31.40 dB. *
1
ADC input
The center level of the input signal is clamped at 2048 LSB (Typ).
Gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (–4.86 dB) to
5.14 times (14.22 dB). *
1
Y-IN input
The input signal is clamped at 280 LSB (Typ) by SYNC Tip clamp.
Automatic offset calibration of PGA and ADC
DC offset compensation feedback for CCD and CDS
Pre-blanking
CDS input operation is protected by separating it from the large input signal.
Digital output is fixed at 32 LSB.
Digital output enable function
Note: 1. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
Offset
calibration
logic
DC offset
feedback
logic
DAC
C3
CDS
AMP
PG
AMP
ADCIN
CDSIN
BLKFB
BLKSH
Gain setting
(register)
Clamp data
(register)
OBP
SH
AMP
BLKC
C4
C2
C1
VRT
Current
DAC
12-bit
ADC
D0 to D11
Figure 1 HD49338F/HF Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
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| HD49338HF | CDS/PGA & 12-bit A/D Converter |
| HD49351BP | CDS/PGA & 10-bit A/D TG Converter |
| HD49351HBP | CDS/PGA & 10-bit A/D TG Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD49338HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter |
| HD49338HNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter |
| HD49338NP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter |
| HD49340F | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
| HD49340HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D Converter |
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