Table 20-8 (2) Bus Timing (S-Mask Versions)
–Preliminary–
Condition B (5-V S-mask):
V
CC
= 5.0 V ±10%, = 2.0 to 16 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications),
T
a
= –40 to +85C (Wide-Range Specifications)
V
CC
= 3.0 to 5.5 V, = 2.0 to 10 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications)
Condition C (3-V S-mask):
Condition D (2.7-V S-mask): V
CC
= 2.7 to 5.5 V, = 2.0 to 8 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications)
Condition D
8 MHz
Min
125
35
35
–
–
–
20
–
–
–
150
Condition C
10 MHz
Min
100
30
30
–
–
–
10
–
–
–
120
Condition B
16 MHz
Min
62.5 500
20
20
–
–
–
5
–
–
–
70
Item
Clock cycle time
Clock pulse width Low
Clock pulse width High
Clock rise time
Clock fall time
Address delay time
Address hold time
Data strobe delay time 1 t
DSD1
Data strobe delay time 2 t
DSD2
Data strobe delay time 3 t
DSD3
Write data strobe
pulse width
Address setup time 1
Address setup time 2
Read data setup time
Read data hold time
Read data access time
Write data delay time
Write data setup time
Write data hold time
Wait setup time
Wait hold time
Bus request setup time
Bus acknowledge
delay time 1
Symbol
t
cyc
t
CL
t
CH
t
Cr
t
Cf
t
AD
t
AH
Max
500
–
–
20
20
60
–
60
60
60
–
Max
500
–
–
20
20
55
–
40
50
50
–
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
10
10
30
–
30
30
30
–
t
DSWW
t
AS1
t
AS2
t
RDS
t
RDH
t
ACC
t
WDD
t
WDS
t
WDH
t
WTS
t
WTH
t
BRQS
t
BACD1
20
80
50
0
–
–
15
25
40
10
40
–
–
–
–
–
190
75
–
–
–
–
–
60
15
65
40
0
–
–
10
20
40
10
40
–
–
–
–
–
160
70
–
–
–
–
–
55
10
30
20
0
–
–
10
10
30
10
30
–
–
–
–
–
100
50
–
–
–
–
–
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
See figure
20-4
See figure
20-5
See figure
20-10
342