Table 15-4 A/D Conversion Time (Single Mode)
CKS = 0
Typ
—
63
—
CKS = 1
Typ
—
31
—
Item
Synchronization delay
Input sampling time
Total A/D conversion time
Symbol
t
D
t
SPL
t
CONV
Min
18
—
259
Max
33
—
274
Min
10
—
131
Max
17
—
138
Note:
Values in the table are numbers of states.
15.4.4 External Triggering of A/D Conversion
A/D conversion can be started by an external trigger input.
External trigger input is enabled at the ADTRG pin when the TRGE bit in the ADCR is set to 1.
Between 1.5 and 2 clock cycles after the ADTRG input goes Low, the ADST bit in the ADCSR
is set to 1 and A/D conversion commences.
The timing of external triggering is shown in figure 15-6.
ADST
ADTRG
A/D conversion
1.0 to 2.0 cycles
Figure 15-6 Timing of Setting of ADST Bit
297