Rev. 0, 07/98, page v of 11
7.2.1
7.2.2
7.2.3
7.2.4
Operation Timing .............................................................................................................. 308
7.3.1
Timer Increment Timing...................................................................................... 308
7.3.2
Output Timing...................................................................................................... 311
Interrupt ............................................................................................................................. 311
Operation in System Stop Mode........................................................................................ 312
Reset Operation ................................................................................................................. 312
Precautions ........................................................................................................................ 313
Timer up-counter (TCNT: TCNTH, TCNTL) .................................................... 304
Timer Constant Register (TCONR: TCONRH, TCONRL)................................ 305
Timer Control/Status Register (TCSR)................................................................ 306
Timer Expand Prescale Register (TEPR)............................................................. 307
7.3
7.4
7.5
7.6
7.7
Section 8
8.1
Wait Controller
................................................................................................ 315
Overview............................................................................................................................ 315
8.1.1
Functions.............................................................................................................. 315
8.1.2
Configuration and Operation................................................................................ 315
Registers............................................................................................................................ 316
8.2.1
Physical Address Boundary Registers 0, 1 (PABR0, PABR1)............................ 316
8.2.2
Wait Control Registers L, M, H (WCRL, WCRM, WCRH) ............................... 321
Operation ........................................................................................................................... 324
8.3.1
Wait State Insertion Using the WAIT Line.......................................................... 324
8.3.2
Wait State Insertion Using the Register ............................................................... 325
Operation in System Stop Mode........................................................................................ 325
Reset Operation ................................................................................................................. 325
Precautions ........................................................................................................................ 325
8.2
8.3
8.4
8.5
8.6
Section 9
9.1
Application Examples
................................................................................... 327
Application Examples........................................................................................................ 327
9.1.1
Serial Data Transfer by MPU and DMAC........................................................... 327
9.1.2
Transmission by Programmed I/O (Bi-Sync Mode)............................................ 328
9.1.3
Reception by Programmed I/O (Bi-Sync Mode).................................................. 331
9.1.4
Transmission in DMA Chained-Block Transfer Mode
(Bit Synchronous HDLC Mode).......................................................................... 334
9.1.5
Reception in DMA Chained-Block Transfer Mode
(Bit Synchronous HDLC Mode).......................................................................... 336
Application Circuits........................................................................................................... 338
9.2.1
System Configuration Example............................................................................ 338
9.2.2
Bus Arbitration Block .......................................................................................... 338
9.2
Section 10 Electrical Characteristics
.............................................................................. 341
10.1
Electrical Characteristics of HD64570CP and HD64570F................................................ 341
10.1.1 Absolute Maximum Ratings................................................................................. 341
10.1.2 DC Characteristics................................................................................................ 342