vi
10.1.4 Register configuration .......................................................................................... 220
10.2 Register Descriptions......................................................................................................... 221
10.2.1 Receive shift register (RSR)................................................................................. 221
10.2.2 Receive data register (RDR)................................................................................. 221
10.2.3 Transmit shift register (TSR)................................................................................ 222
10.2.4 Transmit data register (TDR)................................................................................ 222
10.2.5 Serial mode register (SMR).................................................................................. 223
10.2.6 Serial control register 3 (SCR3)............................................................................ 226
10.2.7 Serial status register (SSR)................................................................................... 230
10.2.8 Bit rate register (BRR).......................................................................................... 234
10.2.9 Clock stop register 1 (CKSTPR1) ........................................................................ 239
10.2.10 Serial Port Control Register (SPCR).................................................................... 240
10.3 Operation............................................................................................................................ 241
10.3.1 Overview............................................................................................................... 241
10.3.2 Operation in Asynchronous Mode........................................................................ 245
10.3.3 Operation in Synchronous Mode.......................................................................... 254
10.3.4 Multiprocessor Communication Function............................................................ 261
10.4 Interrupts............................................................................................................................ 268
10.5 Application Notes.............................................................................................................. 269
Section 11 10-Bit PWM
...................................................................................................... 275
11.1 Overview............................................................................................................................ 275
11.1.1 Features................................................................................................................. 275
11.1.2 Block Diagram...................................................................................................... 276
11.1.3 Pin Configuration.................................................................................................. 276
11.1.4 Register Configuration.......................................................................................... 277
11.2 Register Descriptions......................................................................................................... 278
11.2.1 PWM Control Register (PWCRm)....................................................................... 278
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)...................................... 279
11.2.3 Clock Stop Register 2 (CKSTPR2)...................................................................... 279
11.3 Operation............................................................................................................................ 281
11.3.1 Operation .............................................................................................................. 281
11.3.2 PWM Operation Modes........................................................................................ 282
Section 12 A/D Converter
.................................................................................................. 283
12.1 Overview............................................................................................................................ 283
12.1.1 Features................................................................................................................. 283
12.1.2 Block Diagram...................................................................................................... 284
12.1.3 Pin Configuration.................................................................................................. 285
12.1.4 Register Configuration.......................................................................................... 285
12.2 Register Descriptions......................................................................................................... 286
12.2.1 A/D Result Registers (ADRRH, ADRRL)........................................................... 286
12.2.2 A/D Mode Register (AMR).................................................................................. 286