iv
6.1.3
6.1.4
Register Descriptions......................................................................................................... 138
6.2.1
Bus Control Register (BCR) ................................................................................ 138
6.2.2
Wait State Control Register (WSCR)................................................................... 139
Overview of Bus Control................................................................................................... 141
6.3.1
Bus Specifications................................................................................................ 141
6.3.2
Advanced Mode.................................................................................................... 142
6.3.3
Normal Mode........................................................................................................ 142
6.3.4
I/O Select Signal................................................................................................... 142
Basic Bus Interface............................................................................................................ 143
6.4.1
Overview.............................................................................................................. 143
6.4.2
Data Size and Data Alignment............................................................................. 143
6.4.3
Valid Strobes........................................................................................................ 145
6.4.4
Basic Timing........................................................................................................ 146
6.4.5
Wait Control......................................................................................................... 154
Burst ROM Interface ......................................................................................................... 156
6.5.1
Overview.............................................................................................................. 156
6.5.2
Basic Timing........................................................................................................ 156
6.5.3
Wait Control......................................................................................................... 157
Idle Cycle........................................................................................................................... 158
6.6.1
Operation.............................................................................................................. 158
6.6.2
Pin States in Idle Cycle ........................................................................................ 159
Bus Arbitration.................................................................................................................. 159
6.7.1
Overview.............................................................................................................. 159
6.7.2
Operation.............................................................................................................. 159
6.7.3
Bus Transfer Timing ............................................................................................ 160
Pin Configuration ................................................................................................. 137
Register Configuration ......................................................................................... 137
6.2
6.3
6.4
6.5
6.6
6.7
Section 7
7.1
Data Transfer Controller
.............................................................................. 161
Overview............................................................................................................................ 161
7.1.1
Features ................................................................................................................ 161
7.1.2
Block Diagram...................................................................................................... 162
7.1.3
Register Configuration ......................................................................................... 163
Register Descriptions......................................................................................................... 164
7.2.1
DTC Mode Register A (MRA)............................................................................. 164
7.2.2
DTC Mode Register B (MRB)............................................................................. 166
7.2.3
DTC Source Address Register (SAR).................................................................. 167
7.2.4
DTC Destination Address Register (DAR).......................................................... 167
7.2.5
DTC Transfer Count Register A (CRA) .............................................................. 167
7.2.6
DTC Transfer Count Register B (CRB)............................................................... 168
7.2.7
DTC Enable Registers (DTCER) ......................................................................... 168
7.2.8
DTC Vector Register (DTVECR)........................................................................ 169
7.2.9
Module Stop Control Register (MSTPCR).......................................................... 170
7.2