Table A-4 Number of Cycles per Instruction (cont)
Instruction Branch
Fetch
I
Stack
Byte Data Word Data Internal
Access
L
M
Addr. Read Operation Access
J
K
Operation
N
Instruction Mnemonic
DEC
DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DIVXS
DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU
DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV
EEPMOV.B
EEPMOV.W
2
2
2n + 2
*
2
2n + 2
*
2
EXTS
EXTS.W Rd
EXTS.L ERd
1
1
EXTU
EXTU.W Rd
EXTU.L ERd
1
1
INC
INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP
JMP @ERn
2
JMP @aa:24
2
2
JMP @@aa:8 Normal
*
1
2
1
2
Advanced 2
2
2
JSR
JSR @ERn
Normal
*
1
2
1
Advanced 2
2
JSR @aa:24
Normal
*
1
2
1
2
Advanced 2
2
2
JSR @@aa:8 Normal
*
1
2
1
1
Advanced 2
2
2
LDC
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR 3
LDC @(d:24, ERs), CCR 5
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
1
1
2
1
1
1
1
1
1
2
3
4
2
Notes: 1. Not available in the H8/3048 Series.
2. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each.
732