參數(shù)資料
型號(hào): HD66110ST
廠商: Hitachi,Ltd.
英文描述: Column Driver(大液晶顯示平面的LCD驅(qū)動(dòng)器)
中文描述: 列驅(qū)動(dòng)器(大液晶顯示平面的液晶驅(qū)動(dòng)器)
文件頁(yè)數(shù): 16/21頁(yè)
文件大?。?/td> 84K
代理商: HD66110ST
HD66110ST
16
AC Characteristics 1 (V
CC
= 2.7 to 4.5V, VCD–GND = 14 to 40V, and T
a
= –30 to +75
°
C, unless
otherwise noted)
Item
Symbol
Pins
Min
Max
Unit
Notes
Clock cycle time
t
CYC
t
CWH2
t
CWL2
t
CWH1
t
SCL
t
HCL
t
r
t
f
t
DS
t
DH
t
CM
CL2
100
ns
Clock high-level width 1
CL2
37
ns
Clock low-level width
CL2
37
ns
Clock high-level width 2
CL1
50
ns
Clock setup time
CL1, CL2
100
ns
Clock hold time
CL1, CL2
100
ns
Clock rise time
CL1, CL2
50
ns
2
Clock fall time
CL1, CL2
50
ns
2
Data setup time
D0–D7, CL2
35
ns
Data hold time
D0–D7, CL2
35
ns
M phase difference time
Notes: 1. The load must be less than 30 pF between
EI/O2
and
EI/O1
connections of HD66110STs.
2. t
r
, t
f
< (t
cyc
–t
CWH2
–t
CWL2
)/2 and t
r
, t
f
50 ns
M, CL1
300
ns
AC Characteristics 2 (V
CC
= 5
±
10%, VLCD–GND = 14 to 40V, and T
a
= –30 to +75
°
C, unless
otherwise noted)
Item
Symbol
Pins
Min
Max
Unit
Notes
Clock cycle time
t
CVC
t
CWH2
t
CWL2
t
CWH1
t
SCL
t
HCL
t
r
t
f
t
DS
t
DH
t
CM
CL2
83
ns
Clock high-level width 1
CL2
20
ns
Clock low-level width
CL2
20
ns
Clock high-level width 2
CL1
50
ns
Clock setup time
CL1, CL2
100
ns
Clock hold time
CL1, CL2
100
ns
Clock rise time
CL1, CL2
50
ns
2
Clock fall time
CL1, CL2
50
ns
2
Data setup time
D0–D7, CL2
10
ns
Data hold time
D0–D7, CL2
10
ns
M phase difference time
Notes: 1. The load must be less than 30 pF between
EI/O2
and
EI/O1
connections of HD66110STs.
2. t
r
, t
f
< (t
cyc
–t
CWH2
–t
CWL2
)/2 and t
r
, t
f
50 ns
M, CL1
300
ns
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