參數(shù)資料
型號: HD66330T
廠商: Hitachi,Ltd.
英文描述: 64-Level Gray Scale Driver for TFT Liquid Crystal Display(TFT LCD的64級灰度驅動器)
中文描述: 64級灰度的TFT液晶顯示驅動程序(TFT液晶顯示器的64級灰度驅動器)
文件頁數(shù): 11/21頁
文件大?。?/td> 140K
代理商: HD66330T
HD66330T
1526
Relationship between Display Data and Output Voltage
The HD66330T outputs 64-level gray scale voltage generated by 9 levels of LCD drive power supply
voltage and 6-bit digital data. The figure below shows the relationship among the input voltages from the
LCD drive power supply circuit, digital codes, and output voltages.
Display Data
Output Voltage
Display Data
Output Voltage
Di5 Di4 Di3 Di2 Di1 Di0
1st Phase
2nd Phase
Di5 Di4 Di3 Di2 Di1 Di0
1st Phase
2nd Phase
0
0
0
0
0
0
V1
V0 + 1/8
×
(V1–V0)
V0 + 2/8
×
(V1–V0)
V0 + 3/8
×
(V1–V0)
V0 + 4/8
×
(V1–V0)
V0 + 5/8
×
(V1–V0)
V0 + 6/8
×
(V1–V0)
V0 + 7/8
×
(V1–V0)
1
0
0
0
0
0
V5
V4 + 1/8
×
(V5–V4)
V4 + 2/8
×
(V5–V4)
V4 + 3/8
×
(V5–V4)
V4 + 4/8
×
(V5–V4)
V4 + 5/8
×
(V5–V4)
V4 + 6/8
×
(V5–V4)
V4 + 7/8
×
(V5–V4)
0
0
0
0
0
1
V1
1
0
0
0
0
1
V5
0
0
0
0
1
0
V1
1
0
0
0
1
0
V5
0
0
0
0
1
1
V1
1
0
0
0
1
1
V5
0
0
0
1
0
0
V1
1
0
0
1
0
0
V5
0
0
0
1
0
1
V1
1
0
0
1
0
1
V5
0
0
0
1
1
0
V1
1
0
0
1
1
0
V5
0
0
0
1
1
1
V1
V1
1
0
0
1
1
1
V5
V5
0
0
1
0
0
0
V2
V1 + 1/8
×
(V2–V1)
V1 + 2/8
×
(V2–V1)
V1 + 3/8
×
(V2–V1)
V1 + 4/8
×
(V2–V1)
V1 + 5/8
×
(V2–V1)
V1 + 6/8
×
(V2–V1)
V1 + 7/8
×
(V2–V1)
1
0
1
0
0
0
V6
V5 + 1/8
×
(V6–V5)
V5 + 2/8
×
(V6–V5)
V5 + 3/8
×
(V6–V5)
V5 + 4/8
×
(V6–V5)
V5 + 5/8
×
(V6–V5)
V5 + 6/8
×
(V6–V5)
V5 + 7/8
×
(V6–V5)
0
0
1
0
0
1
V2
1
0
1
0
0
1
V6
0
0
1
0
1
0
V2
1
0
1
0
1
0
V6
0
0
1
0
1
1
V2
1
0
1
0
1
1
V6
0
0
1
1
0
0
V2
1
0
1
1
0
0
V6
0
0
1
1
0
1
V2
1
0
1
1
0
1
V6
0
0
1
1
1
0
V2
1
0
1
1
1
0
V6
0
0
1
1
1
1
V2
V2
1
0
1
1
1
1
V6
V6
0
1
0
0
0
0
V3
V2 + 1/8
×
(V3–V2)
V2 + 2/8
×
(V3–V2)
V2 + 3/8
×
(V3–V2)
V2 + 4/8
×
(V3–V2)
V2 + 5/8
×
(V3–V2)
V2 + 6/8
×
(V3–V2)
V2 + 7/8
×
(V3–V2)
1
1
0
0
0
0
V7
V6 + 1/8
×
(V7–V6)
V6 + 2/8
×
(V7–V6)
V6 + 3/8
×
(V7–V6)
V6 + 4/8
×
(V7–V6)
V6 + 5/8
×
(V7–V6)
V6 + 6/8
×
(V7–V6)
V6 + 7/8
×
(V7–V6)
0
1
0
0
0
1
V3
1
1
0
0
0
1
V7
0
1
0
0
1
0
V3
1
1
0
0
1
0
V7
0
1
0
0
1
1
V3
1
1
0
0
1
1
V7
0
1
0
1
0
0
V3
1
1
0
1
0
0
V7
0
1
0
1
0
1
V3
1
1
0
1
0
1
V7
0
1
0
1
1
0
V3
1
1
0
1
1
0
V7
0
1
0
1
1
1
V3
V3
1
1
0
1
1
1
V7
V7
0
1
1
0
0
0
V4
V3 + 1/8
×
(V4–V3)
V3 + 2/8
×
(V4–V3)
V3 + 3/8
×
(V4–V3)
V3 + 4/8
×
(V4–V3)
V3 + 5/8
×
(V4–V3)
V3 + 6/8
×
(V4–V3)
V3 + 7/8
×
(V4–V3)
1
1
1
0
0
0
V8
V7 + 1/8
×
(V8–V7)
V7 + 2/8
×
(V8–V7)
V7 + 3/8
×
(V8–V7)
V7 + 4/8
×
(V8–V7)
V7 + 5/8
×
(V8–V7)
V7 + 6/8
×
(V8–V7)
V7 + 7/8
×
(V8–V7)
0
1
1
0
0
1
V4
1
1
1
0
0
1
V8
0
1
1
0
1
0
V4
1
1
1
0
1
0
V8
0
1
1
0
1
1
V4
1
1
1
0
1
1
V8
0
1
1
1
0
0
V4
1
1
1
1
0
0
V8
0
1
1
1
0
1
V4
1
1
1
1
0
1
V8
0
1
1
1
1
0
V4
1
1
1
1
1
0
V8
0
Note:
1
1
1st phase: The period in which 2-phase control signal CL4 is high and high output current
operation is performed.
2nd phase: The period in which 2-phase control signal CL4 is low and low output current operation
is performed.
1
1
1
V4
V4
1
1
1
1
1
1
V8
V8
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