參數(shù)資料
型號: HD66421TB0
廠商: Hitachi,Ltd.
英文描述: (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)
中文描述: (內(nèi)存提供160通道4級灰度的點陣圖形液晶顯示驅(qū)動程序)
文件頁數(shù): 36/46頁
文件大?。?/td> 201K
代理商: HD66421TB0
Preliminary
Rev. 1.1E '99.02.10
HD66421
Internal Registers
The HD66421 has one index register and 18 data
registers, all of which can be accessed
asynchronously with the internal clock. All the
registers except the display memory access
register are write-only. Accessing unused bits or
addresses affects nothing; unused bits should be
set to 0 when written to.
Index Register (IR):
The index register
(figure 32) selects one of 18 data registers. The
index register itself is selected when both the
CS and RS signals are low. Data bits 7 to 5
are unused; they should be set to 0 when
written to.
Control Register 1 (R0):
Control register 1
(figure 33) controls general operations of the
HD66421. Each bit has its own function as
described below.
RMW bit
RMW = l: Read-modify-write mode
Address is incremented only after
write access
RMW = 0: Address is incremented after both
write and read accesses
DISP bit
DISP = 1: Display on
DISP = 0: Display off (all LCD driver output
pins output VLCD level)
STBY bit
STBY = l: Internal operation and oscillation halt;
display off
STBY = 0: Normal operation
PWR bit
PWR = l: Output high level from DCON terminal
PWR = 0: Output low level from DCON terminal
This bit controls the external power supply for
LCD driving outputs.
AMP bit
AMP = 1: OP amp enable
AMP = 0: OP amp disable
REV bit
REV = 1: Reverse display
REV = 0: Normal display
HOLT bit
HOLT = l : Internal operation stops
HOLT = 0: Internal operation starts
ADC bit
ADC = l: Data in X address H'0 is output from
SEG160; row signals depend on duty.
ADC = 0: Data in X address H'0 is output from
SEG1; row signals are scanned from
COM1.
Figure 32 Index Register (IR)
Data bit
Set value
7
6
5
4
3
2
1
0
Figure 33 Control Register 1 (R0)
RMW DISP
STBY
PWR
AMP
REV
HOLT
ADC
Data bit
Set value
7
6
5
4
3
2
1
0
Register number
36
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